Synopsys certified its digital and analog EDA flows on TSMC's A14 process and completed 64G UCIe IP tape-outs on TSMC's 2nm and 3nm nodes, part of a broader joint announcement around TSMC's Open Innov…
Nvidia's next-generation Rubin Ultra accelerator will ship with 192GB of HBM per GPU, down from 288GB in standard Rubin and B300, according to SemiAnalysis, which first reported the change. SemiAnalys…
TSMC plans to double its CoWoS advanced packaging capacity to 260,000 wafers per month by 2028, up from an estimated 130,000 by the end of 2026, according to 科技新報 TechNews. The current CoWoS bottlenec…
Advanced packaging, particularly TSMC's CoWoS technology, is the true bottleneck in AI hardware, not GPU design, according to an analysis of the AI supply chain. The scarcity of CoWoS capacity, driven…
TSMC's yield issues in advanced HBM packaging, affecting InFO and CoWoS processes, threaten AI accelerator supply and expose risks of over-reliance on Taiwan, creating an opportunity for Intel Foundry…
SK hynix is collaborating with TSMC and Intel Foundry to integrate its HBM4 memory into advanced packaging technologies, including Intel's EMIB, as disclosed at Hot Chips 2026. The collaboration aims …
Bernstein projects the global server market will exceed $1 trillion by 2028, driven by accelerating AI infrastructure spending, according to its Q2 2026 AI tracker report released on August 3, 2026. T…
Sandisk and SK Hynix are developing high-bandwidth flash (HBF) memory technology that could boost GPU accelerator memory capacity from hundreds of gigabytes to terabytes by stacking NAND flash layers,…
TSMC is developing an EMIB-like advanced packaging technology to compete with Intel's Embedded Multi-die Interconnect Bridge, according to sources close to The Information. The company's existing CoWo…
TSMC is developing a new chip packaging technology called CoPoS (Chip-on-Panel-on-Substrate) that replaces traditional circular 300mm wafers with rectangular 310×310 mm panels to increase usable surfa…
TSMC's Arizona expansion aims to alleviate the AI hardware bottleneck by diversifying geographic risk and increasing capacity for advanced 3nm and 2nm processes, as well as CoWoS packaging. The move i…
TSMC is building two new advanced packaging plants at Chiayi Science Park in southern Taiwan, bringing the total to four facilities that are projected to generate over 300 billion Taiwan dollars ($9.3…
TSMC reported a record monthly revenue of 442.68 billion NTD ($13.75 billion) in June 2026, a 67.9% increase year-over-year driven by AI data center expansion. The company also began high-volume manuf…
ASE Technology raised its 2026 capital expenditure target to $8.5 billion, up from $7 billion in February, as AI chip packaging demand continues to outpace supply. The company expects its advanced pac…
At TSMC's European Technology Symposium, Kevin Zhang, TSMC's senior vice president, stated that wafer-level packaging technologies like CoWoS currently offer superior interconnection density for the l…
TSMC Deputy Co-COO Kevin Zhang stated the company is not concerned about Intel's packaging technology competition during TSMC's North America Technology Symposium on April 22, 2026. Zhang acknowledged…
Intel Foundry’s facility in Rio Rancho, New Mexico, is advancing toward becoming the world’s first factory to achieve mass production of glass substrates, a next-generation chip packaging technology c…
MediaTek has integrated Intel's EMIB chip packaging technology alongside TSMC's CoWoS and SoIC services for its AI chip designs, making it one of the few semiconductor designers to dual-source advance…
Memory's share of AI chip component costs rose from 52% to 63% between Q1 2024 and Q4 2025, according to an analysis of Nvidia, AMD, Google, and Amazon chips. Total component spending on AI chips grew…