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MediaTek adopts Intel’s advanced chip packaging alongside TSMC’s services

MediaTek has integrated Intel's EMIB chip packaging technology alongside TSMC's CoWoS and SoIC services for its AI chip designs, making it one of the few semiconductor designers to dual-source advanced packaging. The move addresses capacity bottlenecks at TSMC's CoWoS lines, which have struggled to meet surging demand from hyperscalers and chip designers. MediaTek's strategy, driven by a projected doubling of its data center AI chip revenue to $2 billion by 2026, allows customers to bypass TSMC's packaging constraints by using Intel's larger-scale EMIB packages.

read2 min publishedMay 29, 2026

The chipmaker's dual-sourcing strategy for AI silicon reflects both soaring demand and real capacity bottlenecks at TSMC.

MediaTek is now designing AI chips that use advanced packaging from both Intel and TSMC. It’s one of the few semiconductor designers in the world doing so, and the move says a lot about where the AI hardware supply chain is heading.

The company has integrated Intel’s Embedded Multi-die Interconnect Bridge, known as EMIB, alongside TSMC’s CoWoS and SoIC packaging technologies. MediaTek can now stitch together multiple chip dies into a single high-performance package using two completely different manufacturing ecosystems.

Why MediaTek went dual-source #

The short answer is capacity. TSMC’s CoWoS packaging has been running into supply constraints, and every major hyperscaler and chip designer wants CoWoS capacity.

MediaTek’s solution was to not wait in line. By qualifying Intel’s EMIB as a viable alternative for 2.5D chip integration, the company gives its customers, particularly cloud and data center operators, a second option when TSMC’s packaging lines are booked solid.

Marvell has also been exploring Intel EMIB as an alternative to TSMC’s constrained CoWoS offerings. MediaTek’s public confirmation that it now supports both ecosystems makes it a notable case study in how the semiconductor industry is diversifying its supply chains under AI-driven pressure.

The specific project driving this appears to be a training-focused TPU design built on TSMC’s N3P process node, linked to Google’s tensor processing unit roadmap. Even when the chip itself is fabricated at TSMC, the packaging step, where multiple dies get connected into one module, can happen elsewhere.

The numbers behind the pivot #

MediaTek recently doubled its 2026 revenue forecast for data center AI chips, raising the target from $1 billion to $2 billion.

On the packaging technology side, Intel’s EMIB is targeting larger package sizes, aiming for up to 8x reticle by 2026. Bigger packages can accommodate more chiplets, more memory, and more compute. TSMC’s current CoWoS offerings have physical size limitations that EMIB is specifically designed to exceed.

Disclosure: This article was edited by Editorial Team. For more information on how we create and review content, see our

Editorial Policy.

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