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13:24
2026-06-11
eetimes.com
ai-chips

RISC-V Targets Data Centers, Edge AI, Space

RISC-V International announced at the RISC-V Summit Europe 2026 in Bologna that its open-standard instruction set architecture has matured beyond microcontrollers and now targets data centers, edge AI…

14:22
2026-06-10
eetimes.com
artificial-intelligence

Massive AI Storage Demand Creates a New Memory Wall

The "Memory Wall" bottleneck, originally coined in the 1990s to describe the speed gap between processors and DRAM, has re-emerged in the AI era as DRAM and high-bandwidth memory (HBM) struggle to mee…

07:47
2026-06-10
eetimes.com
ai-infrastructure

AI-Driven Memory Shortage Upends IT Budgets

The rapid buildout of AI infrastructure has created a structural shortage of DRAM and NAND flash memory, causing enterprise IT budgets to become unpredictable and server costs to rise by over 125% in …

17:00
2026-06-09
eetimes.com
ai-chips

Rethinking the Logic-Routing Tradeoff in FPGAs

Efinix has launched the Titanium Edge family of FPGAs for edge AI applications, based on soft or hard RISC-V cores with AI instruction extensions. The company's XLR logic cell dynamically reconfigures…

14:30
2026-06-03
eetimes.com
ai-infrastructure

LPDDR6 Roadmap Leads to the Data Center

JEDEC is updating its LPDDR6 memory standard to include features tailored for AI data centers, including a narrower x6 per-die interface to double memory densities and a new SOCAMM2 module standard. T…

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