Full disclosure: I am writing this series in my role as program chair of the DAC Engineering Tracks, hoping to give you plenty of reasons to join us in Long Beach, not as part of my day job at Synopsys. The observations, the map, and any opinions are mine alone and do not represent my employer.
Every summer, our industry gets one week in which the entire chip design ecosystem assembles in a single building. This year, the 63rd Design Automation Conference (DAC), now officially “The Chips to Systems Conference,” moves to Long Beach, California, and I would argue there has never been a better year to walk the exhibit floor with intent. The reason is simple: The AI transformation of chip design that we have all been writing about, debating, and occasionally rolling our eyes at is no longer an abstraction on analyst slides; it is real and is visible on the DAC 2026 show floor.
My friend Simon Davidmann—a simulation and verification pioneer, co-creator of Superlog/SystemVerilog, and founder of Imperas, where I worked for him from 2008 to 2010—framed the moment well. (Imperas was one of six EDA companies that he founded or helped shape, all of which were acquired, starting with Gateway Design Automation [Verilog!].) First in his EDN essay on what EDA problem is worth solving with AI, and then in an EE Times piece by Nitin Dahad following DVCon, Simon argued that today’s agentic AI mostly automates the workflows that humans already do, connecting existing tools with scripts, agents, and APIs—useful, measurable, real, but still organized around human-shaped silos. The “magic,” he said, will come from a holistic approach that rethinks the toolchain itself, so AI can reason across the whole stack rather than shuttling between four decades of accumulated fragments. He calls today’s agentic AI a band-aid on the way to a genuine reset.
The earlier EDN essay sorts our ecosystem into four camps: the big-three vendors branding incremental heuristics as platforms, the agentic startups smoothing workflow pain atop legacy tools, giant users such as Samsung and Nvidia quietly building private AI stacks on everyone’s engines, and the sidelined academics and foundation-model labs—each optimizing for its own incentives. Simon has since given the two underlying issues names. One is “Davidmann’s Dilemma,” whereby every camp acting rationally guarantees the collectively wrong outcome. The other is “Davidmann’s Test,” which asks, “Does it change what you can verify, or just how fast you run what you already verify?” If it does only the latter, it fails the test.
View All The Dilemma is not an accusation; it is a systems observation. The incumbents rationally protect the platform gravity and signoff trust they spent 40 years earning. The agentic startups rationally approach the sharpest workflow pain their APIs can reach—it is what customers pay for this quarter. The giant users rationally keep their best AI behind the firewall, because their design flows are their IP—and, as Simon added, they learn from all their own data, which outsiders can only envy. And academia rationally publishes what open benchmarks can measure—rarely the industrial-scale problem. Four rational strategies, one collectively wrong outcome: Everyone shovels faster, and nobody changes the shape of the mountain.
Keep the four camps in mind as you read on: They map onto the layers I introduce below. Fittingly, Simon himself will be on stage at DAC twice to argue the point—on Wednesday’s Exhibitor Forum panel and at Tuesday’s Accellera luncheon (more on both below).
The DAC 2026 landscape: one stack, read from the foundations up
The map for the DAC 2026 AI landscape reads like the design flow it serves, and every layer carries a letter for easy reference as you walk. At the bottom sit 31 companies enabling the compute infrastructure (F): IP, foundries, chips, assembly, and systems—the layer everything else runs on. Above it, five companies provide design data and infrastructure (E): IP lifecycle management, MCP, and RAG servers—the governed context every agent stands on. Then the layer where some of the arguments live: AI models and model foundations—three companies with frontier LLMs, silicon foundation models (A), 10 companies with custom domain models (B), and the user’s own. Some vendors and users train, some wrap, some optimize. On top sit the 26 providers with classic EDA tools (G), spanning the five flow stages from idea to silicon to systems. Twenty companies show agentic point-tool enhancements (D) woven into those tools, one cockpit at a time. Spanning the whole width above them, the agentic AI flows (C), 22 companies are orchestrating across tool boundaries. And at the top, the developer use cases, home of the Engineering Track’s user experiences and of Part 2. Read bottom-up, it is a supply chain of trust: Every claim at the top must be signed off by something below.
Two elements sit alongside the stack: security (S), the eight companies enabling the trust layer that must hold at every level, and standards and interfaces—Accellera’s formats, Si2’s OpenAccess and LLM Benchmarking Coalition, and the MCP-style agent-to-tool interfaces. They are the seams between the layers, and seams, as Simon pointed out, are not normally company-driven.
In total with the “Big Three”—Cadence Design Systems, Synopsys, and Siemens EDA—we have about 130 vendors on the floor and contributing to the Engineering Sessions and panels at DAC 2026.
A musing on levels of automation: L1 to L5 is only half a claim
All of the big vendors have borrowed the SAE’s L1-to-L5 automation ladder from the driving world: Synopsys pitches AgentEngineer workflows at L4; Cadence has long described five levels of autonomy for chip design. Fair enough: The ladder usefully separates assistance from autonomy. But in automotive, the level is only half of the claim. The other half is the operational design domain (ODD): An L4 robotaxi is L4 within a geofenced city, a weather envelope, a speed limit. In EDA, I would argue, the ODD equivalent is the scope of the design flow the autonomy touches, precisely what separates categories D and C in the landscape. An L4 inside a single tool cockpit is Category D: real autonomy, narrow domain. An L4 across the flow is category C, and a vastly harder ODD, because every tool boundary crossed adds failure modes the way every unmapped intersection does. So the booth question you should be asking is not “what level are you?” but “L4 within what ODD?”
AI models come in many shapes and sizes: one spectrum, two extremes
One more categorization worth carrying in your pocket, orthogonal to the letters: How deep does a company’s relationship with its models actually go? At one extreme sits Cognichip—not exhibiting, but present last year on panels—which trains its own physics-informed foundation model (ACI) on governed, designer-generated, and synthetic chip design data. Its CPO, Stelios Theovanitis, argues publicly that fine-tuning general-purpose models on chip data “is not really AI.” At the other extreme sit companies such as MooresLabAI, which openly names Azure OpenAI and AWS Anthropic as the intelligence behind its VerifAgent and CoverageAgent—perhaps the floor’s cleanest disclosure that the model is from a frontier lab and the differentiation is the orchestration. Neither extreme is wrong; they are opposite bets on where value accrues. Between them, stretch the fine-tuners—ChipAgents, Architect Labs—and the many companies whose base model is, diplomatically, undisclosed. Wraps, fine-tunes, trains themselves—three tiers worth probing at every booth.
Walking the categories: arguments behind the letters
What follows is the walk at the level of argument—what each category is betting on, and what I would debate at its booths—with a few examples each. The complete booth-by-booth tour lives in the appendix, the aisle view here, the floor plan there.
The Big Three are the pole that everything else is defined against. Cadence, Synopsys, and Siemens EDA own the flows, the formats, the foundry certifications, and, above all, the signoff trust that every reset must displace and every orchestrator must borrow. Their shared response to both insurgencies: Weave agents into the platform gravity well, so “which model signs off your chip” resolves to “ours, inside our platform.” The debate here is Davidmann’s Test itself: Agents woven into the platform demonstrably speed up what the platform already verifies, but does platform gravity ever change what can be verified, or does it perfect the shovel?
Category A—the reset bets—is deliberately short: companies that train their own silicon foundation models. Ricursive Intelligence, founded by AlphaChip co-creators, goes furthest. Its model performs placement itself, replacing a P&R engine’s algorithmic core rather than calling it; Normal Computing approaches the flow from the formal side with auto-formalization; Cognichip trains physics-informed models on governed and synthetic data. The shared thesis is about data, not just models: No internet-scale corpus of chip design exists, so open training data converges everyone to open-model capability; durable differentiation requires data nobody else has. The debate: The distance between a declared full-flow to tape-out ambition and production silicon signed off by an owned model remains the biggest unproven step on the floor. The giant users belong to this category in spirit, as Google’s AlphaChip lineage and Nvidia’s internal EDA research are foundation-model programs. If the reset arrives, it may arrive first behind a hyperscaler’s firewall, which is Davidmann’s Dilemma in its sharpest form.
Category B—custom domain models at one point of the flow—trains its own models, too, but here, the model is the product, it serves one stage, and the flow around it survives. The quiet strategic insight is that physics-first training sidesteps the data problem entirely. Quilter grades its reinforcement learning for PCB layout against electromagnetics and manufacturability rather than human precedent, and Mach42 keeps a golden simulator in the loop to check every neural-network surrogate prediction. That trusted-verifier-around-a-fast-learned-model pattern recurs across the category and is its best answer to the accuracy question. It is also the most testable corner of the floor—the claims are numeric, speedups, and deviation percentages, not vibes. The debate: Is narrow and deep the durable position, or does it get absorbed from both sides—frontier models widening above, platforms bundling equivalent point AI below?
Category C—the crowded middle—did not exist at this scale even two DACs ago, and it is Davidmann’s band-aid camp, except the band-aids now carry production numbers. ChipAgents claims a PCIe root cause and patch found in 10 minutes versus four to eight hours of human effort; Verkor.io’s Design Conductor built a Linux-capable RISC-V core in 12 hours, a milestone IEEE Spectrum covered; Bronco AI will present DVBench, a production-grade benchmark for design verification AI—a category accused of demo-ware starting to fund its own measurement. Two observations frame the debate. First, many of these founders are AI people who found EDA, not EDA people who found AI, which cuts both ways: fresh eyes on 40-year-old assumptions and occasional innocence about why those assumptions exist. Second, the category’s economics are the Dilemma in miniature: Attacking the sharpest pain today’s APIs can reach is the rational per-quarter strategy and the one that leaves the mountain’s shape unchanged. The question I will ask at every booth in this layer: What survives when the frontier labs’ next model release absorbs the orchestration layer? Expect consolidation; walk it this year while the energy lasts.
Category D—AI-enhanced classical EDA—is the narrow-ODD layer of the SAE musing: real autonomy, one cockpit at a time, and a deeper bench than the headlines suggest. The most genuine AI here is often the least glamorous: AMIQ EDA’s grounded assistant and MCP server come with one of the floor’s cleanest disclosures of which models sit underneath. Two candor notes sharpen the debate: The productivity multipliers in this layer are vendor-reported, and Blue Pearl has published the floor’s rare counter-narrative, a white paper arguing LLMs lack the determinism for signoff linting. The interesting argument is whether deep-and-narrow autonomy is not the consolation prize but the trustworthy path: A bounded domain is auditable in a way a flow-spanning agent is not.
Category E—the connective tissue—is small, unglamorous, and where Davidmann’s holistic argument lives or dies: AI can only reason across the whole flow if the whole flow’s data is connected. Perforce makes it explicit, pairing IP lifecycle management with RAG and an MCP server. The one question to ask every vendor here: Read versus write—can external agents merely query these systems or mutate design data through them? Whoever governs the agent writes governs the flow, and that governance battle has barely begun.
Category F—the compute infrastructure—reminds you that the hyperscalers wear two hats: substrate for everyone’s AI and among the world’s most demanding chip design houses. Google will present how Alphabet tapes out its own data center silicon on an agent-driven cloud EDA stack; Amazon shows up costumed as Amazon Leo, its satellite constellation with custom silicon aboard. The layer also carries the labor thread: Outsourced design verification is the work that Category C automates first, making every service firm’s AI announcement partly a hedge against its own business model—and the physics thread. However smart the agents get, physics does not negotiate. The debate: Does the cloud stay a neutral substrate for everyone’s agents or become one more gravity well?
The rails—security, standards, and the honesty section—own the arguments no single booth can settle. On security, the sharpest question of the year: Who audits the agents themselves—their model provenance, their access scope, what leaves the perimeter in their prompts? An AI that writes RTL is also an AI that can write vulnerable RTL. On standards, Si2’s LLM Benchmarking Coalition is the industry’s most serious attempt to make AI-for-EDA claims comparable, and the open question is whether agent-to-tool interoperability gets standardized at all or simply inherited from whatever MCP becomes. And the honesty section: Twenty-six exhibitors landed in a bucket I bluntly labeled “Non-AI”—real, often-excellent tools differentiated by algorithms, GPU acceleration, or open source rather than machine learning; Real Intent makes the principled case that signoff must be deterministic and repeatable by design. Per Davidmann’s Test, a deterministic tool that changes what you can verify beats a probabilistic one that only runs faster—the most contrarian sentence on the floor, and possibly the truest.
Why this year, why in person
Here is my honest read: The DVCon question—band-aid or reset?—will not be settled by any single session in Long Beach. But DAC 2026 is the first conference where both answers exhibit at production quality: incumbents with deployed LLM flows and honest lessons learned, insurgents with benchmarks and taped-out proof points, foundation-model builders funded to attempt the rebuild, and the connective-tissue and trust layers quietly deciding whether any of it can be believed at signoff.
A landscape, unlike a slide, rewards walking, and so does Davidmann’s Test: Apply it booth by booth and see how the answers cluster. The DAC Pavilion keeps the honest arguments coming all week: “Agentic AI in EDA: Who’s in Control?” on Monday, “Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?” and “Is EDA AI Delivering on Its ROI Promise?” on Tuesday. The capstone is Wednesday’s Exhibitor Forum panel, “Harnessing AI for SoC Verification: Disruptive or Collaborative?”—Tom Fitzpatrick moderating and Simon Davidmann on the panel, one day after he takes the same argument to the Accellera luncheon. And Monday’s Exhibitor Forum alone traverses the entire stack above in a single room, from Cadence’s production-LLM lessons to Normal Computing’s formal foundations.
And fittingly, for a conference about everything from AI transforming design to building AI chips, you can let AI plan the trip itself: DAC Explorer matches your interests to sessions across the program and builds you a personalized schedule—think of it as Expedia for your DAC journey, except every destination is in the same building, the only layovers are coffee breaks, and the middle seat next to you might be a future co-author, vendor, or customer, and Nitin Dahad is right there taking one of his now-famous selfies with you.
Finally, given that this went long, we have created a printable version of the walkthrough here [Link to pdf] that has a longer description of the walkthrough to study on your plane ride.
This is Part 1 of 3: Part 2 covers the Engineering Track’s users building their own AI on vendor engines, juxtaposed with their audits of the vendors’ AI; Part 3 tours the sessions on creating the AI chips themselves. Registration is at dac.com, and the full session details cited above are in the official DAC 2026 program. See you in Long Beach.
Frank Schirrmeister writes about semiconductors, EDA, and system design. He serves as program chair of the DAC Engineering Track; this series is written in that capacity, not on behalf of his employer, Synopsys. Opinions are his own.
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