CEA-Leti Looks Beyond SRAM and DRAM as AI Reshapes the Memory Roadmap

wpnews.pro

As AI pushes more data through processors, accelerators, and embedded systems, CEA-Leti is rethinking the memory roadmap. The institute is not betting on a single emerging technology to replace SRAM, DRAM, or NAND flash. Instead, it sees new memories filling the gaps to create a more diverse hierarchy adapted to AI’s need for more capacity, lower energy, and closer proximity to compute.

For François Andrieu, head of the memory lab at CEA-Leti and a Leti fellow, the roadmap now follows two main tracks. “One is rooted in Leti’s long-standing work on embedded nonvolatile memory [eNVM], mainly for microcontroller applications,” he told EE Times. “The other is driven by AI, where the challenge is to keep more information close to the compute engines that need it.”

Two paths in the roadmap

The first path remains important. Devices increasingly need online updates, and microcontrollers require more memory without necessarily moving to the most advanced and expensive logic nodes. Leti has worked on resistive RAM with Weebit Nano, whose customers include DB Hitek, onsemi, and Texas Instruments. Leti has also worked on next-generation phase-change memory with STMicroelectronics. Andrieu said these technologies already have a place in the embedded-memory roadmap, including applications at 28 nm and 18 nm.

The second path is rapidly growing in importance. Although AI is often discussed in terms of large data centers, Andrieu said similar memory pressure is appearing in edge devices. Sensors and processors are becoming more tightly coupled as systems move toward physical AI—devices that sense their environment.

View All That changes the function of memory. AI systems need low-energy reads for inference, persistent storage for model weights, and larger working memories close to processors. In many cases, the goal is not to replace existing memory but to insert new technologies into the hierarchy where SRAM, DRAM, and NAND do not provide the right mix of density, speed, endurance, persistence, and energy efficiency.

Some emerging memories could provide embedded nonvolatility for code and data retention. Others could store AI weights close to compute. Others could act as working memories for inference, context, or key-value cache functions. Still others could support compute-in-memory or alternative computing models that use the physics of the memory device itself.

“We will not replace SRAM, DRAM, or NAND,” Andrieu said. “But there are opportunities to add new, complementary memories.”

FeRAM moves toward industrial relevance

One of the most important candidates in Leti’s current work is ferroelectric memory (FeRAM). Andrieu said the research institute is collaborating with the company FMC on this and is pushing FeRAM because it could offer a useful combination of density, high endurance, and high speed. “In some applications, designers could trade endurance and speed against the benefit of nonvolatility, moving toward something like a lower-power, nonvolatile DRAM,” he said.

Leti recently demonstrated FeRAM integration in a 22-nm process with a high-aspect-ratio structure intended to improve density. Andrieu described it as the smallest FeRAM integration for an eNVM solution. “The work is significant because it moves FeRAM closer to a manufacturable integration scheme rather than leaving it as an isolated device result,” he said.

While Leti has demonstrated small arrays and is working toward megabit-scale FeRAM integration, Andrieu said further material breakthroughs and adoption by major industrial players will be needed before such technologies can move into products.

For FeRAM, a key challenge is to preserve ferroelectric properties in very thin layers while integrating the material in the back end of line. That integration must respect the thermal budget of the underlying CMOS process. Operating voltage is also a major issue. “Today, the voltage required by some ferroelectric memories remains above the voltage used by core logic, which affects both speed and power,” Andrieu said.

The same pattern applies across the emerging-memory field. Academic research can demonstrate promising devices and materials, but the path to industrial memory is much longer. Materials must be integrated into VLSI flows. Devices must scale into arrays. Arrays must become complete circuits. Manufacturers must then solve variability, reliability, yield, endurance, retention, error correction, operating voltage, and peripheral-circuit integration.

Andrieu said this transition from academic device to industrial technology is precisely where an RTO such as Leti has a role. “Closing that gap is our mission,” he said.

That gap is especially visible in back-end-memory integration. Andrieu noted that many academic demonstrations use flexible process techniques that are useful for exploration but do not translate directly into VLSI manufacturing. Once the memory is placed in a real microelectronics environment, researchers must consider issues such as hydrogen diffusion, oxygen vacancies, and compatibility with back-end-of-line processing.

Data centers create a market pull

For Leti, the roadmap is not just about choosing the best memory material; it’s about showing that the material can survive integration and scaling to operate efficiently with the rest of the system. Andrieu said new memories require a large market if they are to become industrial products. Data centers, with their growing appetite for memory bandwidth, capacity, and energy efficiency, are now one of the few markets large enough to justify the investment.

The complementary approach could be particularly relevant for Europe. If emerging memories can be integrated into the back end of line, they may allow manufacturers to add differentiated capability on top of relatively relaxed CMOS nodes. Rather than competing only at the most advanced front-end logic nodes, European players could exploit memory integration, back-end scaling, and vertical density.

Andrieu said the opportunity for Europe is that back-end-memory integration could allow manufacturers to add differentiated capability on top of relatively relaxed CMOS nodes, rather than competing only through front-end transistor scaling. “This is very interesting, for example, for Europe,” he said.

In that model, Europe would not have to compete solely by building the smallest transistors. It could instead add value by integrating dense, low-power, or nonvolatile memories above established CMOS platforms.

That creates two possible scaling paths: One is conventional lateral scaling, whereby memory density increases by shrinking features in the x-y plane. The other is vertical scaling, whereby memory capacity increases upward through additional layers. Andrieu said both embedded memory and chiplet memory could benefit from relaxed CMOS nodes combined with back-end or vertical integration. He added that because back-end integrated memory allows for easier in-memory computing, power consumption and latency are both further reduced.

Emerging-memory research is often presented as a race to find a universal replacement for incumbent technologies. Leti’s roadmap is more pragmatic: SRAM, DRAM, and NAND remain. Phase-change memory, resistive RAM, FeRAM, and other candidates are inserted where they make architectural and economic sense. Some may serve microcontrollers. Some may support edge AI. Some may address data center inference or working memory.

For CEA-Leti, the future of memory is not a clean handoff from one dominant technology to another. It’s a layered roadmap in which new memories fill the spaces between today’s hierarchy—and increasingly move upward into the back end and the vertical dimension.

CEA-Leti Looks Beyond SRAM and DRAM as AI Reshapes the Memory Roadmap

Two paths in the roadmap

FeRAM moves toward industrial relevance

Data centers create a market pull

See also:

Run your AI side-project on zahid.host