CEA-Leti CEO Sébastien Dauvé told the LID World Summit 2026 in Grenoble, held June 23-25, that architecture—not raw compute—is AI's emerging bottleneck, with data movement, interconnects, power conver…
CEA-Leti program manager Pascal Vivet said 3D stacking and chiplet-based architectures are key to overcoming AI's memory and power density limits, as the institute develops interconnects from 10-micro…
CEA-Leti, Scintil Photonics, and NcodiN are developing photonic interconnects that move optical links inside AI processor packages, from co-packaged optics to nanolasers for photonic interposers. Scin…
CEA-Leti is rethinking the memory roadmap as AI reshapes computing, with François Andrieu, head of the memory lab, saying the institute sees new memories filling gaps rather than replacing SRAM, DRAM,…
Researchers at Leti Innovation Days 2026 identified energy consumption as the primary constraint on AI hardware scaling, with data movement accounting for about 40% of energy use in large language mod…
CEA-Leti CEO Sébastien Dauvé told EE Times that AI's primary bottleneck is architectural, not just energy, as the industry must integrate memory, photonics, communications, and sensing into complex sy…