Researchers at the recent Leti Innovation Days (LID 2026) described a shift in how they think about semiconductor roadmaps. The biggest challenges for the near future are delivering electricity efficiently, moving data with less energy, and removing heat from systems that may run continuously at high utilization.
According to Jean-René Lèquepeys, CTO and deputy CEO of CEA-Leti, scaling up computing systems will require rethinking how they are designed. “Otherwise, they will consume too much energy, making them too costly and unsustainable in the long term,” he told EE Times.
Stephan Guttowski, managing director of Research Fab Microelectronics Germany, or FMD, reached a similar conclusion from the system-integration side. “Miniaturization still helps reduce energy consumption at the chip level, but it’s not enough,” he told EE Times. “At the system level, significant further steps are needed to solve the energy problem.”
AI growth turns energy into the limiting factor
Large AI systems require more than raw arithmetic capability. They require high-bandwidth memory, fast links between processors, efficient power conversion, dense packaging, and cooling systems that can handle rising heat flux. As systems scale by connecting more GPUs and CPUs, the energy cost of moving data and feeding accelerators can become as important as the accelerators themselves.
View All Lèquepeys said the surprise of the past year has been the speed at which data centers became a central semiconductor use case. But he warned that the economic model of AI infrastructure remains fragile.
“The mechanisms for data centers to be economically viable are not really there today because they are very costly in terms of the electricity bill,” he said. “They also require very costly GPUs, along with expensive cooling systems and power devices.”
Guttowski said he was also surprised by the scale of the AI wave. As a hardware specialist, he didn’t expect software progress to create such immediate demand for microelectronics. But the result, he said, is that AI will require microelectronics to be integrated into many more kinds of systems and components.
That software-driven demand is now pushing against the physical limits of hardware deployment. Guttowski said data centers will not be able to keep scaling unless microelectronic systems reduce their power demand. Otherwise, cooling requirements would rise proportionately with compute capacity.
The hardware consequence is clear: AI scaling is increasingly constrained by energy at the system level.
The energy problem is mostly a data-movement problem
For LLM workloads, Lèquepeys said he estimates that data movement, including memory access, accounts for about 40% of energy consumption, while interconnect accounts for about 30%. Compute represents closer to 10%, with power conversion and cooling each around 10%. He stressed that these are workload-dependent estimates. For HPC-like workloads, compute and data movement may be closer to 25% each. The trend, however, is consistent: As AI systems scale, data movement and interconnect pressure increase. Lèquepeys said AI workloads are already memory-bound, meaning processors may not be used at full capacity because data cannot be supplied fast enough.
One answer is to shorten the distance data must travel. Lèquepeys pointed to high-bandwidth memory, 3D integration, near-memory computing, and compute-in-memory as ways to bring memory and processing closer together. With 3D integration, he said, data can move over a short vertical distance rather than a long horizontal distance, improving energy efficiency. In-memory computing goes further by reducing the need to move data at all, though it requires larger memories, new compilers, and schedulers.
HBM is already central to AI accelerators because it stacks DRAM dies vertically and places them close to the processor. Lèquepeys also highlighted resistive RAM as a longer-term candidate for AI because crossbar arrays can perform matrix-vector multiplication using analog computation. The potential advantages are lower energy and massive parallelism, but it comes with a set of challenges, including variability, precision, endurance, and programming.
Guttowski reinforced that advances in packaging will be just as important. Chiplets, 2.5D integration, and 3D technologies allow different functions to be placed closer together, reducing data movement and enabling new system concepts. But he said these approaches bring thermal, mechanical, and electromagnetic-compatibility challenges that must be considered from the start.
Optical communication is another part of the data-movement roadmap. Lèquepeys said electrical interconnects remain superior on-chip and generally inside packages, where distances are short, and optics would require lasers, modulators, and photodetectors. But between packages, boards, and racks, optical links become increasingly attractive as electrical links require equalization, retimers, and higher transmit power.
At rack-to-rack distances and beyond, he said, optics is overwhelmingly superior. The relevant metric is energy per bit. Lèquepeys cited ranges of 3 to 10 picojoules per bit for silicon photonics, adding that GaN microLED-based approaches could get down to around 0.5 picojoules per bit.
Power delivery and cooling become part of chip architecture
The energy barrier is not only about data. It’s also about getting power to the processor efficiently.
Lèquepeys said one of the main losses occurs in the last stage of power conversion, from 54V DC down to roughly 0.7V DC to power an XPU. He said 96% efficiency is achievable while maintaining power density above 200 W/cm³, but only with innovation in power devices and converter architectures.
Wide-bandgap and ultra-wide-bandgap materials are central to that roadmap. Gallium nitride and silicon carbide are already important for high-frequency and high-power conversion. Lèquepeys also pointed to gallium oxide, diamond, and aluminum nitride as longer-term materials with potential for higher voltage, higher temperature, higher switching frequency, and lower leakage.
AI data centers increasingly distribute power at hundreds of volts DC to reduce current and cable losses. But the closer power gets to the chip, the harder conversion becomes. As racks move toward much higher power levels, converter efficiency, power density, and cooling become inseparable.
Guttowski said the substrate should not be treated as a passive carrier. Voltage regulators and passive components can be positioned directly beneath active ICs using embedding technologies, while backside power delivery could open new packaging options.
“The goal is to get power on the chip without too much loss on the way,” he said. “The more we distribute the power converter, the more we can reduce the losses. But it is also a design issue.”
That design issue includes reliability. Guttowski said electrical, thermal, and mechanical design must be closely linked to avoid failure mechanisms created by heat and stress. Cooling concepts may also need to move closer to the semiconductors.
Roadmaps shifting to system-technology co-optimization
Lèquepeys’ roadmap for energy-efficient computing spans 15 technology areas, including new memories, 3D heterogeneous integration, optical and RF links, wide-bandgap power devices, new computing paradigms, dedicated accelerators, alternative architectures, energy-efficient power converters, frugal algorithms, AI-based EDA tools, and system-technology co-optimization.
“No single technology will deliver the value alone,” Lèquepeys said. New memories, 3D integration, optical links, new power devices, new converter topologies, neuromorphic approaches, analog-digital computing, and better algorithms all have to work together.
That’s where Guttowski’s emphasis on system-technology co-optimization, or STCO, becomes important. Processors, memory, interconnects, packaging, power delivery, and cooling cannot be optimized separately if the goal is to reduce total system energy. Improvements in one area can simply move the bottleneck elsewhere.
Guttowski said future design methodologies must connect models, data, and tools across electrical, thermal, mechanical, geometric, cost, reliability, and security domains. Rather than replacing existing CAD tools, STCO should connect them through shared data interfaces so engineers can evaluate tradeoffs across the system.
The next phase of AI hardware development, then, will not be defined only by faster accelerators. It will be defined by how much useful computation systems can extract from each watt—by shortening data paths, placing memory closer to compute, delivering power more efficiently, and designing the package, substrate, interconnects, and cooling system as part of the architecture.
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