In Part 1 of this series, I mapped the DAC 2026 exhibit floor as an AI landscape—a stack read from the compute foundations up through the models, the classic tools, and the agentic layers, with security and standards as the rails alongside. That map answered who is transforming chip design with AI. In Part 2, I showed how users apply AI to design—frequently their own AI, built on the industry’s engines.
This final part asks the questions I deliberately saved for last: What does it take to create the AI chips themselves—the accelerators, the memory systems, the interconnects—and where at DAC do the people who actually do this work share what they have learned? Because amid all the breathless funding announcements for AI that designs chips, it is worth remembering what DAC is actually for: the chips and systems that come out the other end. AI accelerators—both the training engines filling data centers and the inference silicon spreading from cloud to edge—are this year’s headline act, but the same holds for the aerospace and defense systems where chips meet missions, for automotive and for every other domain that turns silicon into something people can use. The agents and flows are the means; the silicon is the point.
The answer, in large part, can be found in the sessions that will be presented with the DAC Engineering Track, where working engineers from the companies designing today’s silicon present what worked, what broke, and what they would do differently—peer-reviewed by other engineers, with no marketing filter. This year, the Track spans 15 sessions with ~90 presentations plus special sessions and poster “Gladiator” battles on the pavilion stage. If Part 1 gave you the map, consider this the guided tour for everyone whose job title involves making AI hardware real.
And a framing to carry with you, borrowed from my friend Simon Davidmann and the same framework, Dilemma, and Test that anchored Part 1: The interesting question is not whether AI helps chip design but whether it works within today’s tool silos or forces a holistic rethink. The AI problem worth solving, according to Simon, is expanding what kinds of hardware-software systems we can verify at all, not merely accelerating the flows we already run. Nothing stresses every silo simultaneously—logic, memory, interconnect, power, thermal, package, software—quite like an AI accelerator. Creating AI chips is the workload that makes Simon’s question urgent.
Start at the top: The demand side speaks
Before descending into methodology, hear from the people whose appetite for compute is reshaping the industry. Qualcomm EVP and CTO Baaziz Achour keynotes on “Design Automation for Emerging AI: From AI Chips to Data Center”—the demand side stating its requirements to the supply side, in plenary. Nvidia’s Timothy Costa opens the conference Sunday evening with a Welcome SKYTalk on AI supercomputing meeting EDA. And the DAC Pavilion’s SkyTalk series runs a daily masterclass on AI silicon: Intel’s Lalitha Immaneni on Monday (“From Silicon to Systems: Heterogeneous Integration as the Engine of AI Performance”), IBM Research’s Huiming Bu on Tuesday (“From 7 nm to 7Å,” a retrospective that looks forward), and the one I would circle twice: Microsoft’s Artour Levin, VP of AI Silicon Engineering, on Wednesday morning with “EDA Opportunities in Building High Performance AI Accelerators.”
Artour’s abstract is worth reading closely, because it is essentially a requirements document from one of the world’s most consequential AI silicon teams. His argument: As accelerators scale from chips to full systems, the hard problems increasingly emerge at theboundaries—between compute, memory, interconnect, and software behavior—exactly where traditional EDA methodologies were not built to operate. He promises practical insight into current EDA limitations at AI scale and the solutions being deployed in production. If you read Part 1’s landscape, you will recognize this as the demand-side echo of Davidmann’s holistic thesis: The boundaries between the silos are where the pain lives.
The IP track: AI building blocks, themselves built by AI
Every AI chip is assembled from standard cells, memories, SerDes, PLLs, and interface IP—Part 1’s “every camp tapes out on somebody’s PLL” layer. What makes this year remarkable is the recursion: The IP itself is now being designed, optimized, and signed off with AI.
Tuesday’s session, “AI-Accelerated IP Libraries: From Optimization to Signoff,” is the concentrated dose. One presentation attacks a limitation so familiar, we forget it is a choice: Standard-cell libraries offer roughly 30 variants per gate type while the theoretical space holds millions, and AI-driven transistor-level sizing that generates tailor-made cell variants per design reports double-digit power and timing improvements on real industrial silicon while staying compatible with standard EDA flows. Others bring adaptive AI to high-sigma standard-cell verification, apply ML to memory-circuit optimization, and use AI to parse hard-IP integration documents into automated checkers, reporting up to two weeks saved and zero requirement omissions, a small preview of the specification-engineering theme from Part 1’s front-end stage. The session closes with the unglamorous but essential guardrails: Intel’s unified library QA framework using Siemens’s Solido Crosscheck and automated Liberty model validation across 1,000+ cells and 30+ PVT corners. The pattern deserves attention: AI accelerates the creative steps, while systematic validation keeps signoff honest—trust and speed advancing together or not at all.
The companion session, “IP Design for Mixed-Signal and High-Speed SoCs,” covers the interfaces that AI systems live or die by: a formal verification approach that caught a deeply buried credit-management bug in PCIe Gen6/7 logic—the bandwidth generations explicitly driven by AI and data center workloads—and a distributed dynamic power-integrity flow for SerDes scaling from 56G through 224G. When your accelerator’s value depends on feeding it data fast enough, this stage matters as much as the compute.
Physics does not negotiate, AI chip edition
Part 1 called physics the boundary where AI meets electrons. Sessions in the Engineering Track show what that means when the chip in question is an AI chip: power densities, current transients, and thermal coupling that break the assumptions our flows grew up with.
The delightfully named session “A Good Grid Can Never be IR-Responsible” is a tour of power delivery at AI scale: hierarchical EMIR analysis for reticle-scale data center SoCs achieving 10× runtime reduction where flat analysis simply saturates; power-supply-network analysis for FCBGA packages in high-power AI applications in which fast di/dt switching breaks traditional PDN assumptions; and a full-stack analysis of 12-high HBM revealing a 442% increase in maximum IR drop compared with single-die analysis, a number that should end any lingering belief that multi-die systems can be signed off die by die. On the Gladiator stage, a poster on backside power delivery reports 19.8% core power reduction and 9.3°C thermal mitigation for next-generation AI processors.
Thermal gets its own session—“Serving Hot 3D-IC on Clean and Cool Plates”—where the standout for me is a Broadcom and Synopsys collaboration on early thermal analysis for face-to-face 3DIC stacking, correlated against post-silicon measurement to within 3°C, alongside an AI-driven methodology that explores hundreds of thermally constrained placement scenarios in heterogeneous chiplet stacks. And Wednesday’s special session, “AI and Multi-die: A Reinforcing Cycle,” names the feedback loop this whole article orbits: AI workloads drive multi-die architectures, and multi-die complexity drives AI-assisted design—each accelerating the other.
The edge, the memory wall, and the lifecycle
Creating AI chips is not only a hyperscaler sport. Monday’s special session, “The Heterogeneous Future of Agentic AGI,” argues that the next leap is bringing agentic AI to the edge on heterogeneous CPU/GPU/NPU platforms, and the Engineering Track backs it with practice: a custom edge NPU delivering 100 GMAC/s in just 200K gates by tuning the ISA and memory architecture to the application. The memory wall, arguably the defining constraint of AI silicon, gets attacked from the exhibitor forum side in the Synopsys-hosted session on computing inside nonvolatile memory with startups such as TetraMem, which Part 1 filed under silicon and IP. And once the AI chip ships, we then follow it into the field: a silicon lifecycle management presentation uses embedded trace, compressible up to 700×, to hunt silent data corruption, with an AI inference engine as the silicon case study.
For the startup-side view of all of the above, Tuesday’s Veriest-hosted exhibitor forum session, “Scaling AI for Chip Design: Platforms and Infrastructure,” features Ricursive’s Anna Goldie on “Closing the Loop Between AI and the Hardware That Fuels It”: the AlphaChip lineage applied to precisely the reinforcing cycle this article describes.
Why this matters, and what comes next
Here is the through-line I hope you take to Long Beach: Creating AI chips stresses the boundaries—between cells and libraries, dies and stacks, chips and packages, silicon and software—and the Engineering Track at DAC 2026 is where practitioners show, with numbers, how those boundaries are being managed today. Some of the answers extend existing flows; some quietly demand the holistic rethink that Simon Davidmann argues for, and a few, held up to Davidmann’s Test, genuinely expand what can be verified at all. All kinds are on stage, presented by the engineers who own the tapeouts.
Part 2 of this series flipped that perspective: Instead of AI chips as the product, it looked at AI as the tool in which users build their own AI on top of vendor EDA engines, such as Samsung’s reinforcement-learning QoS optimization and IBM’s agentic debug flows. Together with Part 1’s landscape, the three parts should give you a complete itinerary.
Registration is at dac.com, and every session mentioned here is in the official DAC 2026 program. See you in Long Beach.
Frank Schirrmeister writes about semiconductors, EDA, and system design. He serves as program chair of the DAC Engineering Track; this series is written in that capacity, not on behalf of his employer, Synopsys. Opinions are his own.
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