Nvidia is extending CUDA support to RISC-V CPUs, requiring server-grade features such as RVA23 compliance, ACPI, PCIe coherency, and peer-to-peer PCIe, according to a Hot Chips 2026 talk. The company …
Alibaba has brought day-zero support for its Qwen-3.8 27B AI model to its RISC-V-based XuanTie C950 chip, achieving 30 tokens per second decode speed and a 1.9-second time to first token. The chip, re…
China is advancing its own open-source technology ecosystem, including artificial intelligence, as part of a national strategy to reduce foreign dependence and gain competitive advantage, according to…
Morphic, a new operating-system experiment by developer who goes by the name Morphic, aims to determine how much of Linux can be stripped away before real software stops working, with the first target…
WCH released the CH32V407 and CH32V467 RISC-V microcontrollers, featuring a 200 MHz QingKe V3V core with RVV vector extensions, integrated 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbp…
Open source hardware is more secure than proprietary chips because it undergoes extensive community stress-testing, enabling rapid patching and verifiable auditability, according to a technical analys…
IREE, an open-source compiler from the IREE project, now compiles machine learning models to native RISC-V CPU code with support for the RISC-V Vector extension (RVV), hand-written microkernels, and d…
Startup Majestic Labs claims its Prometheus server, built with Ignite AI Processing Units and LPDDR6 memory, can deliver up to 128 TB of unified memory and 25.6 TB/s bandwidth, more than 50 times the …
A developer used Anthropic's Claude AI to design a custom RISC-V processor, system-on-chip (SoC), and printed circuit board (PCB), demonstrating how large language models can assist in hardware design…
Beijing aims to add 50,000 petaflops of intelligent computing power in the second half of 2026, pushing total capacity over 130,000 petaflops by year-end, the Beijing Municipal Bureau of Economy and I…
A developer is using large language models to automatically extract architectural parameters from the RISC-V specification, aiming to replace slow and error-prone manual reading. The approach involves…
Researchers have demonstrated the first low-power MCU-based edge device for Automatic License Plate Recognition (ALPR), using a 9-core RISC-V processor (GAP8) and a QVGA ultra-low-power greyscale imag…
Hong Kong Chief Executive John Lee outlined the city's strategy to become a superconnector in the age of AI at the SCMP China Conference, emphasizing AI as a central plank in its first five-year bluep…
Global cooperation on the RISC-V chip architecture remains resilient despite US-China tech rivalry, Alibaba vice-president Qi Xiaoning said at the South China Morning Post's China Conference 2026, not…
OXMIQ Labs, founded by former Intel chief GPU architect Raja Koduri, raised $35 million in Series A funding to scale its OxCore architecture, a licensable GPU core designed to run CUDA and PyTorch cod…
Naja-scope, an MCP server built on the najaeda netlist engine, lets AI agents explore SystemVerilog netlists without pasting source code. In a head-to-head test on the CVA6 RISC-V core, it achieved 17…
GCC 17 has landed support for the SpacemiT X100 RISC-V core, the first widely-available RVA23 profile compliant design, via -mcpu=spacemit-x100 and -mtune=spacemit-x100 targeting. The SpacemiT K3 SoC …
An engineer who writes backend systems shipped an SDK for a microcontroller without ever compiling it on the target chip's compiler. The code was tested only on a host compiler, and when built in the …
Qualcomm is in advanced talks to acquire RISC-V AI chip startup Tenstorrent for up to $10 billion, a move that would give Qualcomm Jim Keller's Blackhole silicon and an open-source inference stack. Th…
The Linux 7.2 kernel merge window has no new ARM64 KVM features, with developers attributing the lack to an overwhelming number of AI-fueled fixes flooding the mailing list. Other architectures like R…