A new paper-thin, flexible AI sticker sensor node called Ghost Edge has been developed, built around the Nordic Semiconductor nRF54L15 wireless SoC. The device uses a flexible printed circuit board to…
A team has built Aiden AI, a physical hardware AI agent device that connects as a standard USB HID device to control any computer without requiring software installation, API access, or permissions. T…
Epic Semi announced the Contrail Compute AIX, the first RISC-V AI execution platform, designed to run AI inference workloads on open-standard RISC-V architecture. The platform aims to provide a flexib…
Efinix has launched the Titanium Edge family of FPGAs for edge AI applications, based on soft or hard RISC-V cores with AI instruction extensions. The company's XLR logic cell dynamically reconfigures…
OpenCV 5.0 was released today as a major update to the open-source computer vision library, featuring a rewritten deep neural network engine and built-in support for large language and vision language…
Google launched Coral, a full-stack platform for edge AI that combines an AI-first hardware architecture with a unified developer experience to enable efficient, local AI processing. The platform prov…
ByteDance, the parent company of TikTok, is developing custom central processing units (CPUs) to power its artificial intelligence infrastructure, as prices for chips from Intel and AMD have surged 10…
The DARE (Digital Autonomy with RISC-V in Europe) initiative, coordinated by the Barcelona Supercomputing Center with 38 partners, is developing open-source chiplet processors for next-generation supe…
Alibaba engineers have successfully ported Android 16 to run on RISC-V architecture, marking a significant step toward reducing reliance on Arm-based processors. The milestone demonstrates the growing…
Espressif has launched two new development kits for its dual-core RISC-V ESP32-S31 chip, designed for advanced IoT and edge AI applications. The ESP32-S31-Function-CoreBoard-1 offers 16 MB of PSRAM, w…
The article details the process of building and loading a RISC-V firmware for the SNESTang FPGA project, choosing the minimal RV32I architecture for its small size and mature toolchain. The firmware, …