The newest GCC 17 compiler code has landed support for
The SpacemiT X100 is notable in making up the primary cores of the SpacemiT K3 SoC as the first widely-available RVA23 profile compliant RISC-V design. The K3 features eight X100 cores clocking up to 2.4GHz plus there are the eight ultra-wide parallel AI computing A100 cores.
Also on the GCC mailing list is
Considering it was just a few days from the spacemit-x100 patch going from the mailing list to working its way into GCC Git, the spacemit-a100 target will presumably also be upstreamed in short order.
In case you missed some of the SpacemiT K3 benchmarking thus far, see
-mcpu=spacemit-x100and*-mtune=spacemit-x100*targeting for the SpacemiT X100 RISC-V core.The SpacemiT X100 is notable in making up the primary cores of the SpacemiT K3 SoC as the first widely-available RVA23 profile compliant RISC-V design. The K3 features eight X100 cores clocking up to 2.4GHz plus there are the eight ultra-wide parallel AI computing A100 cores.
This patchnow upstream in GCC from SpacemiT adds the initial X100 core support.Also on the GCC mailing list is
a patchintroducing the "spacemit-a100" target for -mcpu/-mtune tuning for the A100 cores too."Add the Spacemit-A100 processor to -mcpu/-mtune. The A100 is an in-order, dual-issue core whose microarchitecture is close to the X60, so for now it reuses the Spacemit X60 costs. On the ISA side, the A100 is closest to the X100. The main differences are that it does not implement the H (hypervisor) extension, its vector length is VLEN=1024 (zvl1024b), and it has the xsmtvdotii extension."
Considering it was just a few days from the spacemit-x100 patch going from the mailing list to working its way into GCC Git, the spacemit-a100 target will presumably also be upstreamed in short order.
In case you missed some of the SpacemiT K3 benchmarking thus far, see