South Korean startup Xcena detailed its MX1 CXL Type 3 device at Hot Chips 2026, combining up to 2 TB of DDR5, SSD-backed InfiniteMemory capacity, and more than 1,000 custom RISC-V cores. Xcena chief …
Tiny Vedas released an open-source RISC-V AI accelerator stack whose shipping RTL is a 4-stage pipelined RV32IM processor in SystemVerilog paired with an 8×8 int8 GEMM MMIO accelerator sharing DCCM ov…
Computing pioneer David Patterson, a former UC Berkeley computer science professor and now a distinguished engineer and fellow at Google, said at the AI Infra Summit that Jensen Huang is "unquestionab…
Netherlands-based AI accelerator startup Axelera launched its Europa AI Processing Unit (AIPU), claiming 629 TOPS within a 45-watt power envelope, and will ship it in two PCIe add-in cards: the half-h…
China's Ministry of Industry and Information Technology and the National Development and Reform Commission on Tuesday outlined a five-year plan for electronics and information technology that forecast…
Dave Ditzel, RISC pioneer and founder and former CEO and CTO of Esperanto Technologies, delivered a keynote and AMA on August 25, 2026, in Palo Alto at the Cool Chips - Hot Takes gathering organized b…
At Hot Chips 2026, NVIDIA detailed its plans to bring RISC-V CPUs into its GPU platforms, outlining requirements for CUDA and NVLink Fusion integration. The company highlighted RVA23 profiles and the …
XCENA and Samsung have developed the MX1, a CXL memory expansion device that hosts up to 2 TB of DDR5 memory, supports SSD storage, and includes 3,072 RISC-V cores for data-parallel compute, targeting…
PyTorch Conference North America 2026, scheduled for October 20–21 in San Jose, CA, will feature Core PyTorch sessions covering compiler and runtime internals, distributed communication, device portab…
SiFive has launched a new development server aimed at bringing RISC-V architecture into the datacenter, marking a significant push to compete with established players like Intel and AMD in the server …
SiFive launched the BigSky SF-2U870, a 32-core RISC-V server based on the P870-D cores, on August 24th, providing a development platform for porting Linux and CUDA before custom data-center chips arri…
Nvidia announced at Hot Chips 2026 that CUDA will officially support RISC-V CPUs, making RISC-V the third supported host architecture alongside x86 and ARM, with strict requirements including the RVA2…
Nvidia is extending CUDA support to RISC-V CPUs, requiring server-grade features such as RVA23 compliance, ACPI, PCIe coherency, and peer-to-peer PCIe, according to a Hot Chips 2026 talk. The company …
Alibaba has brought day-zero support for its Qwen-3.8 27B AI model to its RISC-V-based XuanTie C950 chip, achieving 30 tokens per second decode speed and a 1.9-second time to first token. The chip, re…
China is advancing its own open-source technology ecosystem, including artificial intelligence, as part of a national strategy to reduce foreign dependence and gain competitive advantage, according to…
Morphic, a new operating-system experiment by developer who goes by the name Morphic, aims to determine how much of Linux can be stripped away before real software stops working, with the first target…
WCH released the CH32V407 and CH32V467 RISC-V microcontrollers, featuring a 200 MHz QingKe V3V core with RVV vector extensions, integrated 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbp…
Open source hardware is more secure than proprietary chips because it undergoes extensive community stress-testing, enabling rapid patching and verifiable auditability, according to a technical analys…
IREE, an open-source compiler from the IREE project, now compiles machine learning models to native RISC-V CPU code with support for the RISC-V Vector extension (RVV), hand-written microkernels, and d…
Startup Majestic Labs claims its Prometheus server, built with Ignite AI Processing Units and LPDDR6 memory, can deliver up to 128 TB of unified memory and 25.6 TB/s bandwidth, more than 50 times the …