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Dave Ditzel's keynote/AMA on Esperanto's odyssey

Dave Ditzel, RISC pioneer and founder and former CEO and CTO of Esperanto Technologies, delivered a keynote and AMA on August 25, 2026, in Palo Alto at the Cool Chips - Hot Takes gathering organized by AiNEKKO, AIFoundry, OpenHW Foundation, and 10xEngineers, tracing his path from early microprocessors and RISC through Bell Labs, SPARC, Transmeta, Intel, and Esperanto. Ditzel detailed Esperanto's ET-SoC-1, a low-power manycore RISC-V system for AI and HPC with more than 1,000 64-bit RISC-V CPUs on a single chip, custom vector and tensor acceleration, and a large on-chip memory hierarchy, and previewed ET-SoC-2x with higher-throughput ET-Minion2 cores and a chiplet-based architecture on a roadmap from 7nm SoCs to 4nm and 2nm compute fabrics. Over ten years Esperanto developed several RISC-V cores, extensive design-verification work, and a broad set of software tools, parts of which are being carried forward through CORE-ET and AIFoundry's open ET Platform.

read2 min views3 publishedSep 11, 2026
Dave Ditzel's keynote/AMA on Esperanto's odyssey
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On Aug 25, 2026, in Palo Alto, we got together for Cool Chips - Hot Takes, an independent community gathering organized by AiNEKKO, AIFoundry, OpenHW Foundation, and 10xEngineers.

The evening brought together engineers, founders, investors, and friends doing cool things with chips, silicon design, and agentic systems. But before talking about the future we honored the work done at Esperanto Technologies that is now largely open source and fueling the next generations of chip development.

Dave Ditzel, a RISC pioneer and founder and former CEO and CTO of Esperanto Technologies, traced his personal and technical journey from the earliest microprocessors and the origins of RISC through Bell Labs, SPARC, Transmeta, Intel, and finally Esperanto. He explained why Esperanto moved from its own instruction set to RISC-V, and why an open, extensible ISA creates more room for innovative and energy-efficient processor designs.

He then went inside ET-SoC-1, Esperanto’s low-power manycore RISC-V system for AI and HPC: more than 1,000 64-bit RISC-V CPUs on a single chip, custom vector and tensor acceleration, a large on-chip memory hierarchy, and a software stack capable of compiling high-level machine-learning models for the platform. The talk also looked ahead to ET-SoC-2x, its higher-throughput ET-Minion2 cores, chiplet-based architecture, and the broader roadmap from 7nm SoCs to 4nm and 2nm compute fabrics.

The session closed with a candid look at the lessons of turning an ambitious architecture into production silicon — and at what comes next. Over ten years, Esperanto developed several RISC-V cores, extensive design-verification work, and a broad set of software tools. Parts of that work are now being carried forward through CORE-ET and AIFoundry’s open ET Platform, with the hope that more of the ecosystem can become open and useful to the wider RISC-V community over time.

A rare first-person retrospective on RISC, manycore architecture, low-power AI acceleration, and the long road from an idea to working silicon — followed by an open AMA with the people helping to continue that work.

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