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[ARTICLE · art-36793] src=eetimes.com ↗ pub= topic=artificial-intelligence verified=true sentiment=· neutral

Software to Silicon With RISC-V for Physical AI

EE Times moderated a panel with MIPS CEO Sameer Wasson and RISC-V International CEO Andrea Gallo on rethinking chip design for agentic AI. The discussion covered GlobalFoundries' acquisition of MIPS and Synopsys ARC Processor IP, RISC-V becoming the default ISA for new designs, and the shift to software-first architectures.

read1 min views5 publishedJun 22, 2026
Software to Silicon With RISC-V for Physical AI
Image: Eetimes (auto-discovered)

Nitin Dahad of EE Times moderates a panel with Sameer Wasson, CEO of MIPS, by GlobalFoundries, and Andrea Gallo, CEO of RISC-V International, for a conversation on how the industry must rethink chip design for agentic AI. Topics covered:

• GlobalFoundries’ acquisition of MIPS and the recent acquisition of the Synopsys ARC Processor IP solutions business and what it means for customers

• Why RISC-V is becoming the default ISA for new silicon designs

• The shift to software-first, workload-optimized architectures

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