Nvidia announced at Hot Chips 2026 that CUDA will officially support RISC-V CPUs, making RISC-V the third supported host architecture alongside x86 and ARM, with strict requirements including the RVA2…
RISC-V International CEO Andrea Gallo declared at the RISC-V Summit Europe 2026 in Bologna that the open-standard instruction set architecture is now targeting data centers, edge AI, and space explora…
EE Times moderated a panel with MIPS CEO Sameer Wasson and RISC-V International CEO Andrea Gallo on rethinking chip design for agentic AI. The discussion covered GlobalFoundries' acquisition of MIPS a…
RISC-V International announced at the RISC-V Summit Europe 2026 in Bologna that its open-standard instruction set architecture has matured beyond microcontrollers and now targets data centers, edge AI…
A developer's study of computer architecture revealed that the future of artificial intelligence depends on specialized hardware like Tensor Processing Units and Neural Processing Units, as standard C…