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@Verilog

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2024-02-03
nand2mario.github.io
hardware

Adding a Softcore to SNESTang - part 1

The article explains the addition of a softcore CPU to the SNESTang 0.3 FPGA project to handle I/O tasks like USB and file systems, which previously consumed valuable FPGA logic space when implemented…

// co-occurs with top 7 entities
SNESTang 1 NESTang 1 MiSTer 1 MIST 1 Sipeed Tang 1 FAT32 1 ARM 1