The article describes how the author initially used a softcore CPU to improve FPGA gaming cores on the SNESTang but found it limited by slow performance and high resource usage. After collaborating wi…
The article details the process of building and loading a RISC-V firmware for the SNESTang FPGA project, choosing the minimal RV32I architecture for its small size and mature toolchain. The firmware, …
The article explains the addition of a softcore CPU to the SNESTang 0.3 FPGA project to handle I/O tasks like USB and file systems, which previously consumed valuable FPGA logic space when implemented…
The SNESTang 0.3 project ports the Super Nintendo Entertainment System (SNES) to Tang FPGAs, using a phase-based clock design with a main work clock (wclk) at 10.8 MHz to simplify logic and reduce clo…