A developer successfully fitted a diffusion model into 264KB of RAM using a microcontroller and an onboard FPGA, but the parallelized INT8 MAC engines performed worse than the MCU-only implementation …
A 3.16M-parameter transformer running on a $250 FPGA achieves 44 tokens per second by moving the CPU out of the per-token loop, according to a technical blog post detailing the on-chip LLM design. The…
An FPGA-based on-chip LLM decoded replies in 6.6ms, but browser delivery took 100ms; profiling revealed that 58% of the delay came from a host-side loop reading 193 logits per token over /dev/mem. The…
A $250 FPGA-based on-chip LLM project achieved a record 59,965.5 tokens per second with a split-brain N=16 configuration at 200 MHz, according to the developer's blog post. The project, built with han…
A new study from researchers explores optimizing Transformer neural networks for real-time outlier detection in financial time series using FPGAs. The work demonstrates efficient implementation on a P…
Researchers introduced E-SpecFormer (Edge Spectrum monitoring Transformer), an edge-efficient model for end-to-end automatic modulation and covert channel recognition. The Nano variant achieves 86.5% …
Researchers found that FPGA implementations of ML-KEM decapsulation verification leak side-channel information even with higher-order masking, enabling full secret-key recovery. The study compared unp…
Researchers introduced FlexViT, a reconfigurable FPGA accelerator that achieves up to 2.74x speedup for Vision Transformer layers on edge devices. The accelerator uses a hardware-software co-design ap…
BoolSi, a startup founded by a former chip designer, has raised $6M to build a compiler that converts software hotspots into custom hardware accelerators for FPGAs. The tool uses machine learning to l…
A developer implemented a full Transformer with KV cache on an FPGA, achieving over 56,000 tokens per second at only 80 MHz, without using a GPU or CPU. The design was created gate by gate as a custom…
A developer argues that balanced ternary (-1, 0, +1) could replace binary for AI hardware, citing 20× model compression, 3× inference speedup, and 8× power reduction. Microsoft's BitNet b1.58 demonstr…
Researchers at the University of Tennessee and the University of Florida developed a hardware neural network backdoor that can be hidden in custom chips used for edge AI, exploiting vulnerabilities in…
Reiner Pope, CEO of AI chip startup MatX and former Google engineer, delivered a blackboard lecture explaining chip design from basic logic gates to the architectures of GPUs, TPUs, FPGAs, and the hum…
The article summarizes the development of an FPGA-based 80386 core that runs DOS and games at 75 MHz, then shifts focus to analyzing the processor's memory pipeline. It explains that while the 80386's…
The article discusses a challenge with implementing UART communication in FPGAs when the system clock frequencies are not integer multiples of the desired baud rate, leading to imprecise timing and er…
The article describes the memory system of the GBATang, an FPGA-based Game Boy Advance (GBA) core, which combines FPGA block RAM and external SDRAM to replicate the GBA's diverse memory map. Smaller, …
The article details the process of building and loading a RISC-V firmware for the SNESTang FPGA project, choosing the minimal RV32I architecture for its small size and mature toolchain. The firmware, …