The hardware setup included an onboard FPGA, which was used to implement two parallel INT8 MAC engines with 16-bit accumulation. On paper, this should have turbocharged the inference speed. However, this is where the "memory wall" becomes a very real problem. Because the system was hitting a bottleneck with the sheer volume of I/O operations required to feed those engines, the parallelized version actually performed worse than the MCU-only implementation. We're talking about a jump from roughly 70 seconds per image up to 220 seconds. It's a classic example of how raw compute power means nothing if your data pipeline can't keep up.
For anyone looking for a practical tutorial on how to handle such tight constraints, this project highlights a few key technical hurdles:
Memory Bandwidth: The I/O overhead of moving weights and activations between memory and the FPGA engines completely negated the speed gains of the parallel MACs.Heavy Quantization: To fit within the 264KB limit, the model had to be quantized aggressively. This leads to a distinct visual style—lots of noise and "weird" artifacts—since the precision isn't there to maintain smooth gradients.Resolution Limits: Sticking to 32x32 pixels is mandatory here. Even a slight increase in resolution would exponentially increase the memory footprint of the latent space or the activation maps.
Despite the noise and the slow generation times, seeing a diffusion process happen on a microcontroller is a huge win. It proves that you don't always need a massive A100 cluster to experiment with generative AI workflows; sometimes, a deep dive into low-level memory management is more rewarding. It’s less about "production-ready" quality and more about the sheer engineering feat of making the math fit the silicon.
If you want to see the full breakdown and the resulting images, the detailed case study is hosted here:
https://rndbn.vercel.app/sir-pixelot
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