Semiconductor

The Intel 386 processor, introduced in 1985, was the first 32-bit CPU in the x86 architecture and contains numerous registers that provide much faster storage than main memory. The processor's register implementation is …

The article describes the repair of a non-working Commodore PET computer from 1977, part of the "1977 Trinity" of early home computers. The repair was challenging due to multiple failed custom ROM and RAM chips, which ar…

The article explains that the Pentium processor uses microcode, a layer of software underneath machine instructions, to control its circuitry. The Pentium's microcode ROM contains 4,608 micro-instructions, each 90 bits l…

The article describes how the author initially used a softcore CPU to improve FPGA gaming cores on the SNESTang but found it limited by slow performance and high resource usage. After collaborating with Sipeed, they inte…

The article discusses a challenge with implementing UART communication in FPGAs when the system clock frequencies are not integer multiples of the desired baud rate, leading to imprecise timing and errors. The author pre…

The article describes the memory system of the GBATang, an FPGA-based Game Boy Advance (GBA) core, which combines FPGA block RAM and external SDRAM to replicate the GBA's diverse memory map. Smaller, low-latency memories…

The article provides practical tips for using Gowin EDA software and Tang FPGA boards (such as the Tang Nano 20K), emphasizing that the free Pro version should be used over the EDU version. It offers guidance on enabling…

The article describes the development of GBATang, an FPGA core for the Game Boy Advance (GBA) designed for Tang FPGA boards, which began as a port of the MiSTer GBA core but required significant redesign due to the Tang …

The article details the process of building and loading a RISC-V firmware for the SNESTang FPGA project, choosing the minimal RV32I architecture for its small size and mature toolchain. The firmware, which includes a bas…

The article explains the addition of a softcore CPU to the SNESTang 0.3 FPGA project to handle I/O tasks like USB and file systems, which previously consumed valuable FPGA logic space when implemented in Verilog. The cho…

The SNESTang 0.3 project ports the Super Nintendo Entertainment System (SNES) to Tang FPGAs, using a phase-based clock design with a main work clock (wclk) at 10.8 MHz to simplify logic and reduce clock domains. The arch…

Moore's Law has evolved from a 60-year-old observation about transistor density doubling every 18 months into an economic principle focused on the 50% cost reduction of chips per silicon area. Achieving this economic eff…

The article describes the process of extracting and disassembling the microcode ROMs from high-resolution photographs of the Intel 8086 and 8088 dies, revealing the internal instruction sequences of these processors. Key…