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SPPU

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00:00
2024-01-07
nand2mario.github.io
hardware

Design notes for SNESTang 0.3

The SNESTang 0.3 project ports the Super Nintendo Entertainment System (SNES) to Tang FPGAs, using a phase-based clock design with a main work clock (wclk) at 10.8 MHz to simplify logic and reduce clo…

// co-occurs with top 7 entities
SNESTang 1 Tang FPGAs 1 SNES 1 SCPU 1 SSMP 1 SPC700 1 DSP 1
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hardware 1 semiconductor 1 open source 1 developer tools 1