Synopsys’s latest Compute Express Link (CXL) IP offerings target one of AI infrastructure’s most persistent constraints: Memory capacity and bandwidth are struggling to keep pace with increasingly demanding models.
The company’s recently announced CXL 4.0 IP portfolio integrates a controller, IDE security module, silicon-proven physical layer, and verification IP, with support spanning CXL 4.0 and earlier generations of the interconnect.
The AI boom, now entering its inference and agentic era, has intensified long-running pressure on memory. In a briefing with EE Times, Ron Loman, product marketing manager for PCIe and CXL IP at Synopsys, said the bottleneck can be traced back as far as 2012. “There’s never been enough cache on chip. There’s never been enough DRAM accessible.”
CXL, a cache-coherent interconnect built on the PCIe physical layer, enables processors, accelerators, and memory devices to communicate and share resources.
View All Designers, meanwhile, are increasingly turning to multi-die packages, chiplet-based architectures and rack-scale systems to deliver the capacity and bandwidth needed for large language models, recommendation engines, and other memory-intensive applications.
More bandwidth for AI memory expansion
AI workloads have pushed requirements beyond what a single system-on-chip (SoC) can accommodate, making off-chip resources essential. “You have to go off chip to multiple chips,” Loman said.
CXL 4.0 was released in late 2025 and introduced several features to support higher throughput. It doubles bandwidth to 128 GT/s, aligns with PCIe 7.0, preserves CXL 3.x latency, and expands capacity for chip-to-chip communication and larger disaggregated designs.
Loman said bandwidth and port bundling are the two defining features of CXL 4.0.
Bundling addresses a long-standing comparison point between CXL/PCIe and proprietary interconnects, he said. While CXL and PCIe traditionally cap at 16 lanes per port, bundled ports let designers combine multiple 16-lane links; four x16 links can provide more than 2 TB/s of bandwidth, while eight can exceed 4 TB/s.
CXL 4.0 also supports up to four retimers, helping extend signal reach as higher data rates reduce the distance over which channels can operate reliably. Other changes include native x2 link widths and a 256-byte latency-optimized flit intended to increase payload efficiency.
CXL deployment remains uneven
The goal of Synopsys’s CXL IP is to make the protocol easier to adopt.
Loman said CXL 2.0 is in volume production. CXL 3.x, which is aligned with PCIe 6.0 and PAM4 signaling, is only beginning to see broader adoption as the transition from NRZ to PAM4, along with new flit modes, has introduced implementation complexity. “It’s getting out there,” he said. “We’re just starting to see CXL 3 being deployed.”
Synopsys’s CXL 4.0 IP is designed to ease that integration burden. The controller supports CXL 4.0, 3.x, 2.0, and 1.x on a unified architecture, with backward compatibility, bundled ports, port-based routing, and latency-optimized flit support.
Aside from performance related updates, Loman said security has also become a priority as CXL moves into multi-tenant and confidential-computing environments. Synopsys’s IDE security modules provide AES-GCM encryption and authentication with zero-cycle latency overhead in skid mode, along with TSP/TDISP support and FIPS 140-3 readiness.
“With PCIe 7 and CXL 4, we’re seeing an extremely high rate of adoption with IDE and the security aspect,” he said. “People realize that you have to have the security in place and they’re planning for it.”
A broader high-performance IP strategy
CXL 4.0 is one element of Synopsys’s wider high-performance computing IP portfolio, which includes interface IP for UCIe, UALink, Ultra Ethernet, and 224G/448G Ethernet PHYs; foundation IP such as memory compilers and logic libraries; security IP covering root-of-trust, PUF, and post-quantum cryptography; and pre-integrated IP subsystems for accelerators and hyperscaler SoCs.
Disaggregated compute also depends on ecosystem maturity. A fully realized CXL-based system requires compatible CPUs, accelerators, SSDs, memory controllers, switches, and software stacks. Marvell’s recently announced AI memory infrastructure portfolio illustrates how this trend is expanding beyond chip-level integration and includes memory expansion and pooling capabilities that align with Synopsys’s CXL strategy.
Loman said he expects CXL to progress from basic expansion to broader sharing and, eventually, full disaggregated compute.
“I’m pretty bullish that CXL is going to be very widespread,” he said. “Now it’s moved to more memory sharing, and then it’s CXL 4 with added bandwidth—it’s more of a disaggregated compute.”
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