A Kubernetes Dynamic Resource Allocation (DRA) driver makes composable CXL memory a schedulable cluster resource for cross-node KV-cache reuse in LLM serving, according to an arXiv paper (2609.10790v1…
Kioxia presented a Compute Express Link (CXL) module at a Tokyo briefing that uses its XL-Flash NAND to replace some DRAM in AI workloads, claiming it can double memory capacity at the same cost while…
Synopsys has updated its Compute Express Link (CXL) IP portfolio with CXL 4.0 support, targeting AI infrastructure memory bottlenecks. The portfolio integrates a controller, IDE security module, silic…
Marvell Technology Inc. introduced a memory-disaggregation portfolio targeting AI infrastructure bottlenecks, including the Bravera SC6 PCIe 6.0 SSD controller, the Structera CXL family, and Photonic …
Synopsys announced the industry's first complete Compute Express Link (CXL) 4.0 intellectual property suite, including a controller, IDE security modules, a PCIe 7.0-based physical layer, and verifica…