IBM unveiled the world's first sub-1 nanometer chip technology on June 25, 2026, using a new 0.7nm "Nanostack" 3D transistor architecture (also called 7 angstrom). The chip packs nearly 100 billion transistors onto a fingernail-sized die - nearly twice the density of IBM's 2nm chip from 2021. The Nanostack design vertically stacks transistors in 3D, allowing different semiconductor materials per layer to independently optimize performance and power. Published results at VLSI 2026 include 40% SRAM scaling - a memory gain the industry has not seen in over a decade. IBM projects up to 50% more performance or 70% greater energy efficiency vs the 2nm node, and estimates AI accelerators built on 7 angstrom chips could reach ~7,000 TOPS versus today's ~1,500, potentially cutting frontier LLM training from three months to two weeks. Commercial production is targeted in as early as five years.
Stacking the Deck: IBM’s NanoStack and the Sub-1 nm Era