AMD's initial AVX10_V2_AUX ISA support was merged into LLVM 24 Git on Monday, spanning 15,000 lines of new code across 20 patches and exposed in the Clang compiler via the new -mavx10v2aux flag. AVX10…
AMD and Intel's joint AI Compute Extensions specification, ACEv1, was merged into the GCC 17 development branch on September 2, 2026, delivering up to 16 times the compute density of equivalent AVX10 …
Intel and AMD's AI Compute Extensions (ACEv1), the first instruction set the two companies designed together, have landed in the GCC 17 compiler tree with the flag -macev1, enabling open-source compil…
AMD engineer Dipesh Sharma posted patches for the GNU Compiler Collection to add AVX10_V2_AUX ISA support, which includes dedicated data processing and format conversion instructions for accelerating …
The x86 Ecosystem Advisory Group has released a whitepaper and specification for ACE (AI Compute Extensions), a new accelerator type for Intel's AMX instruction set that introduces outer product instr…
Intel engineers posted initial GCC compiler patches for the AI Compute Extensions (ACE), a cross-vendor x86 specification for optimizing AI and machine learning workloads. The ACE specification, devel…
The x86 Ecosystem Advisory Group released the AI Compute Extensions (ACE) Specification on June 15, 2026, defining standardized x86 extensions for matrix multiplication and tile registers to accelerat…
AMD and Intel, through the x86 Ecosystem Advisory Group, are standardizing new matrix math instructions called ACE (AI Computation Extensions) to accelerate AI workloads on x86 processors. ACE introdu…