Intel and AMD’s AI Compute Extensions just stopped being a PDF and became a compiler switch.
The initial enablement patches for the AI Compute Extensions landed in the GCC Git tree on Wednesday, which means the first instruction set Intel and AMD designed together now has an open-source compiler that can actually emit it. Phoronix caught the merge. The switch is -macev1
, and enabling it implicitly pulls in AVX10.1, AVX and AVX2, and the SSE/SSE4 baseline underneath them.
Compilers gain support for unreleased silicon constantly, and on its own that would be a footnote. What makes this one worth stopping on is whose silicon it targets: both of them.
The first thing the x86 alliance has actually shipped #
ACE came out of the x86 Ecosystem Advisory Group, the body Intel and AMD formed in late 2024 and then filled out with Broadcom, Dell, Google, HPE, HP, Lenovo, Meta, Microsoft, Oracle and Red Hat. For most of its life the group has produced announcements about producing things. ACEv1, whose specification went public in June, is the first piece developers can build against, and it is designed to succeed Intel’s Advanced Matrix Extensions with AMD implementing the same thing rather than something adjacent to it.
Anyone who sat through the AVX-512 years understands why that ordering matters. Intel shipped a vector extension, pulled it from consumer parts, watched AMD implement it properly years later, and left software vendors guessing about what they could assume for most of a decade. Writing the specification first and the silicon second is the correction to that, and it only counts if the toolchains agree.
What ACEv1 looks like underneath #
The whitepaper defines eight tile registers, each 512 bits wide by 16 rows, plus a block-scale register: a tighter and less configurable arrangement than AMX offered. Supported formats are the ones inference actually leans on now, INT8 and BF16 alongside MXFP8 and MXINT8. The figure the group leads with is compute density. An ACE outer product, it claims, does roughly 16 times the work of an equivalent AVX10 multiply-accumulate while consuming the same number of input vectors, because it accumulates into a tile register in two dimensions instead of a vector register in one.
ACE is not binary-compatible with AMX, so nothing recompiles for free. It is, however, grafted onto the way AMX is already exposed to programmers, which should keep the porting work closer to mechanical than to a rewrite.
Compiler now, hardware later #
GCC 17.1 is due around March or April, so the toolchain will be sitting ready well before anything can run what it emits. No shipping processor executes ACE today. It is aimed at Intel’s Diamond Rapids generation and a future Zen core, and neither vendor has pinned a date to it. Intel compiler engineers have been posting ACEv1 patches to the GCC list since July with AMD engineers reviewing, and the parallel work for LLVM and Clang is moving through its own pull request.
More enablement will almost certainly land before GCC 17 goes stable, since what merged on Wednesday is explicitly the initial cut rather than the finished job. The useful signal is not performance, because there is nothing to benchmark yet. It is that two companies who spent thirty years using instruction sets as weapons against each other now have a shared one far enough along that the compiler people are arguing about flag names. That tends to be more durable than a slide.