Earlier this month Intel compiler engineers posted
The AVX10_V2_AUX instruction set adds dedicated data processing and format conversion for helping accelerate AI workloads. AVX10_V2_AUX adds onto AVX10 with instructions for converting standard data types to compressed data formats like FP4 and FP6, support for additional OCP microscaling formats, new rounding modes, and more. All the capabilities are outlined in the
Complementing the initial ACE enablement patches for GCC earlier this month from Intel and showing the close collaboration between AMD and Intel engineers around ACE/AVX10 as part of the x86 Ecosystem Advisory Group, AMD engineer Dipesh Sharma posted the latest GNU Compiler Collection patches for plumbing the AVX10_V2_AUX ISA support.
The
initial GCC compiler patches for the AI Compute Extensions "ACE"that was born out of the x86 Ecosystem Advisory Group to augment AVX and scalar code with new capabilities for AI/ML workloads. Now as part of that an AMD compiler engineer posted patches over the weekend for AVX10_V2_AUX ISA support.The AVX10_V2_AUX instruction set adds dedicated data processing and format conversion for helping accelerate AI workloads. AVX10_V2_AUX adds onto AVX10 with instructions for converting standard data types to compressed data formats like FP4 and FP6, support for additional OCP microscaling formats, new rounding modes, and more. All the capabilities are outlined in the
ACE v1 specification.Complementing the initial ACE enablement patches for GCC earlier this month from Intel and showing the close collaboration between AMD and Intel engineers around ACE/AVX10 as part of the x86 Ecosystem Advisory Group, AMD engineer Dipesh Sharma posted the latest GNU Compiler Collection patches for plumbing the AVX10_V2_AUX ISA support.
"This series of 7 patches aims to add support for cpuid detection, builtins and intrinsics for AVX10_V2_AUX instructions.
AVX10_V2_AUX is a new ISA for x86, supporting converts between FP32-FP8, FP8-FP4, FP8-FP6, and vice-versa."
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