Apple's M4 chip, first shipped in the 2024 iPad Pro, is the first publicly available device to support ARM's scalable matrix extension (SME), replacing the proprietary AMX instruction set Apple has us…
A new paper and model from researcher George Diamos show that a block-routed mixture-of-experts with 128 experts and 3.65 million active parameters achieves 93% on in-context induction and 90% on posi…
Apple's Accelerate framework outperforms GitHub Copilot-generated BLAS Level 3 dtrsm routines on Apple M1 and M2 chips, with performance jumps at matrix sizes that are multiples of 8 attributed to the…
AMD and Intel have co-authored the ACE (AI Compute Extensions) specification, a jointly owned matrix ISA for x86 that freezes a new instruction set aimed at inference-friendly formats and outer-produc…
The x86 Ecosystem Advisory Group has released a whitepaper and specification for ACE (AI Compute Extensions), a new accelerator type for Intel's AMX instruction set that introduces outer product instr…
Intel engineers posted initial GCC compiler patches for the AI Compute Extensions (ACE), a cross-vendor x86 specification for optimizing AI and machine learning workloads. The ACE specification, devel…