The upcoming update to JEDEC’s LPDDR6 will squeeze in several features that address the memory’s increasing popularity in AI data centers.
For years, LPDDR was associated with smartphones, tablets, and ultra-thin laptops, but now a great deal of supply is being eaten up by memory-hungry AI data centers as they look to reduce power consumption Since releasing the “foundational” JESD209 6 in July 2025, JEDEC’s JC 42.6 Subcommittee has been focused on extending the LPDDR6 standard beyond mobile platforms to support selected data center and accelerated computing workloads that need power-efficient, high-capacity memory.
Increasing performance while reducing power consumption is fundamental to any JEDEC memory standard, Hung Vuong, chair of the JC-42.6 Subcommittee for Low Power Memories, said in a briefing with EE Times. Data center customers are especially interested in LPDDR. “This revision of LPDDR6 will focus a lot of features on their needs,” Vuong said.
View All One key feature will be a narrower x6 per-die interface, which enables higher capacities, said Osamu Nagashima, the subcommittee’s vice-chair. As far as bandwidth goes, it’s not so much of a big jump—perhaps 10 to 20% improvement from the previous iteration. “They can double the densities,” he said.
Moving to a non-binary interface width and an additional x6 sub-channel mode allows more die per package and higher memory capacities per component and per channel.
Nagashima said the goal is to reach 512GB density, which is beyond the current LPDDR5/5X maximum, to address the ever-growing memory capacity requirements of AI training and inference workloads.
The upcoming update will also include an LPDDR6 SOCAMM2 module standard, designed to advance the compact, serviceable module form factor and offer a clear upgrade path from today’s LPDDR5X SOCAMM2 modules. SOCAMM is well-suited to address AI systems’ energy and space constraints by offering 2.5× the bandwidth of conventional modules, while consuming about one-third less energy.
Earlier this year, Micron Technology released its 256GB SOCAMM2, a data center–class modular LPDDR5X memory module for AI infrastructure.
JEDEC is also nearing completion of a standard for LPDDR6 processing-in-memory (LPDDR6 PIM) technology, which complements the broader LPDDR6 roadmap.
Vuong said the LPDDR6‑PIM embeds compute logic directly inside the memory chip, letting the memory perform calculations instead of just storing data. “The idea is to offload some processing into the memory.”
Nagashima said this reduces data movement between CPU/GPU and RAM, which is the main bottleneck for AI workloads. while reducing power use.
Vuong said LPDDR has been transitioning to become a data center memory over the last five years—it’s gone from being primarily a mobile, solder-on solution for smartphones to moving into client computing as companies such as Dell, Lenovo, and HP saw the value of LPDDR5 technology.
He said LPDDR6, as well as SOCAMM, has caught the attention of data center customers as power consumption becomes an increasingly important metric. “AI and data centers are really driving—or straining—the ecosystem right now.”
Vuong said there’s been significant pressure from those users to update the LPDDR6 standard, but also a lot of cooperation to advance it. “Most of the features are defined already,” he said. “We’re just crossing the Ts, dotting the Is, and making sure we didn’t miss anything.”
See also:
[LPDDR6 Balances Performance, Power and Security](https://www.eetimes.com/lpddr6-balances-performance-power-and-security/)
[AI to Drive Surge in Memory Prices Through 2026](https://www.eetimes.com/ai-to-drive-surge-in-memory-prices-through-2026/)
[Majestic Labs Raises $100M for Memory Pooling AI Server](https://www.eetimes.com/majestic-labs-raises-100m-for-memory-pooling-ai-server/)