Tiny Vedas released an open-source RISC-V AI accelerator stack whose shipping RTL is a 4-stage pipelined RV32IM processor in SystemVerilog paired with an 8×8 int8 GEMM MMIO accelerator sharing DCCM ov…
OpenAI is hiring a Research Engineer for AI for Chip Design in San Francisco at a salary of $380,000 to $500,000 per year, a range the job board reports sits 93% above the $228,000 median for AI Agent…
Miguel9554 released Mate IR, an intermediate representation for synthesizable RTL that includes a nearly complete SystemVerilog compiler and simulator, aiming to address inefficiencies in traditional …
Naja-scope, an MCP server built on the najaeda netlist engine, lets AI agents explore SystemVerilog netlists without pasting source code. In a head-to-head test on the CVA6 RISC-V core, it achieved 17…
The article discusses the 80386 processor's improved protection model, which added paging, a flat 32-bit address space, and Virtual 8086 mode to make protected mode usable after the 80286's unpopular …
The article describes the author's project to build an 80386-compatible processor core in SystemVerilog using original Intel microcode, with real mode operational and over 10,000 test cases passing. I…
The z8086 is a compact, FPGA-friendly 8086/8088 processor core that runs original Intel microcode by loading a recovered 512x21 ROM, rather than hand-coding individual instructions. Written in about 2…