A technical overview of co-packaged optics (CPO) for scale-up AI compute details the packaging architectures, photonic integrated circuit (PIC) materials, laser options, and electrical IC (EIC) design…
High bandwidth memory (HBM) is hitting scaling limits driven primarily by thermal gradients across the stack, according to a technical deep dive that cites JEDEC standards and Samsung's HBM4 architect…
OpenAI presented the architecture of Jalapeno, its general-purpose AI inference accelerator, at the Hot Chips 2026 conference, detailing a design built for end-to-end optimization rather than peak "sh…
Semiconductor analyst firm Silicon Codesign published Part 1 of a system-level overview of scale-up AI infrastructure racks, focused on network architecture, ahead of the Hot Interconnects 2026 and Ho…
SRAM serves as the staging ground for KV Cache values written from HBM in LLM inference, and its size directly determines the maximum local data available to local compute, according to a technical de…