The true fragility of the semiconductor supply chain

Supply chains · Graph theory · Semiconductors A graph-theoretic look at semiconductor supply-chain chokepoints

The semiconductor industry arguably has the most critical supply chain in the world. Every modern AI accelerator takes a route that spans the globe. Quartz mined in North Carolina is grown into ingots in Japan, sliced into wafers, exposed by a Dutch lithography machine to ultraviolet light, etched with chemicals from a handful of Japanese firms, fabbed in Taiwan, and finally packaged onto a memory stack made in South Korea. Pull one node out and the chain can topple. Reporters know this anecdotally. I wanted to know whether graph theory could show, mathematically, which companies carry the most load.

The idea here is simple. A handful of network metrics, applied to a directed weighted graph of suppliers, fabs, and consumers, are enough to surface the chokepoints that economists and journalists have been worrying about. Some of the answers are predictable (TSMC). Some are less so (a Japanese photoresist company). This also turns into a useful tour through where the math is honest about the supply chain and where it lies, since several of the network's most “critical” nodes look surprisingly substitutable to the math even when they would be catastrophic to lose in real life. I come back to that gap in the discussion.

First, I built a representative graph from public data. Second, I computed two classical centralities (degree and betweenness), the clustering coefficient as a structural sanity check, and a flow-based “node load” metric. Third, I ran some node-removal scenarios, both individual firms and country-wide failures, and ended with the Albert–Barabási random-vs-targeted attack experiment. Finally, I discuss what the network's structure says about policy.

Background and Related Work #

The relevant graph-theory ideas come from two well-known literatures. Scale-free networks [1] are graphs whose degree distribution follows a power law. A small number of “hubs” connect to many other nodes, and most nodes have just a handful of links. Many real networks, from the World Wide Web to airline routes, have this property. The prediction relevant to my case is that scale-free networks are robust to random failures (most nodes are minor) but extraordinarily fragile to targeted attacks on the hubs [2]. I tested this directly in the robustness section by comparing how the chain's flow capacity decays under random node removal versus targeted removal of the most-loaded nodes. Small-world networks [3] add high local clustering on top of short global path lengths. The clustering side of that story does not really apply here, because a strongly layered DAG cannot have the triangles that clustering measures, but I'll say a bit more about why in the results.

Two strands of supply-chain research are also worth flagging. Sheffi's work on supply-chain resilience [4] popularised the idea that optimising for cost has hollowed out redundancy, leaving critical production concentrated at a few sites. More recently, policy reports from CSIS and the EU JRC [5, 6] have catalogued specific semiconductor chokepoints by hand (ASML's EUV monopoly, Taiwan's foundry concentration, the post-2022 Ukrainian neon disruption, and the Spruce Pine quartz mines that feed essentially every silicon ingot on Earth.) None of those papers, though, frame the chain as a graph and apply the standard centrality machinery. That is the contribution this project tries to make. I took the policy literature's chokepoints as ground truth and asked whether centrality measures rediscover them from structure alone.

Data and Network Construction #

I modeled the chain as a directed weighted graph G = (V, E, c) where nodes V are companies or commodity sources, edges E are flows of goods or intellectual property, and the capacity function c: E → [0,1] is each supplier's global market share for that link. The graph is layered into seven tiers (L₀ … L₆) corresponding to the physical pipeline from raw inputs to final consumers. The table below lists the layers and node counts.

| Layer | What it is | Nodes |

|---|---|---|
| L <sub>0</sub> | Raw inputs (helium, neon, krypton, xenon, high-purity quartz) | 16 | 
| L <sub>1</sub> | Industrial-gas distributors (Linde, Air Liquide, …) | 6 | 
| L <sub>2</sub> | Wafers and chemicals (Shin-Etsu, JSR, TOK, …) | 10 | 
| L <sub>3</sub> | Equipment (ASML, AMAT, Lam, TEL, KLA, …) | 9 | 
| L <sub>4</sub> | Fabs (TSMC, Samsung, SK hynix, …) | 14 | 
| L <sub>5</sub> | Advanced packaging (TSMC CoWoS, in-house lines, OSATs) | 5 | 
| L <sub>6</sub> | Consumers (NVIDIA, AMD, hyperscalers) | 8 | 

| Total | | 68 |

The full graph has 68 nodes and 446 edges. Capacities are 2024–2025 market shares pulled from public sources, like TrendForce for foundry and HBM share, USGS for raw-material production, ASML's investor reports for lithography shipments, and JRC and CSIS for photoresist and gas concentration. Where shares were unavailable (most notably for some Japanese photoresist makers and a few Qatar gas offtake contracts) I used informed estimates. Edges are directed downstream, so a typical path runs Spruce Pine quartz → Shin-Etsu wafer → TSMC fab → TSMC CoWoS → NVIDIA.

A note on TSMC CoWoS. CoWoS (Chip-on-Wafer-on-Substrate) is not a separate company. It is TSMC's proprietary 2.5D advanced packaging technology, and the only reason it shows up as its own node here is that it has a different bottleneck from the rest of TSMC. The CoWoS line runs at a separate facility, has its own capacity ceiling, and for AI chips it is that ceiling, not foundry capacity, that is the binding constraint. So I treated CoWoS as a node so the math can see the constraint as a constraint. The same logic explains why Samsung Foundry (L₄) and Samsung's 2.5D/3D packaging (L₅) are separate nodes.

Limitations. This is not a perfect 1:1 industry map. (a) Sub-tier suppliers (e.g. the small Japanese chemical firms that make the chemistry behind the photoresists) are collapsed into their first-tier customer. (b) IP-flow edges (the chip designer to foundry mask handoff) are not modelled separately from goods-flow edges. (c) Shares for privately negotiated long-term contracts are estimated. I don't expect these gaps to change the structural findings, which depend on who connects to whom rather than on any single estimate (see the sanity check in the discussion).

Methodology #

I computed three classical centralities plus a flow-based metric, and I ran two stress tests on the structure (single-set node removals and a random-vs-targeted attack curve). In all cases I reported values for the “core” graph (everything in the table above) and excluded two synthetic nodes (super_source, super_sink) that I added only when computing maximum flow.

Degree centrality. For a node v in a graph with n nodes,

deg(v)n − 1 This is the simplest answer to “who has the most direct connections?” I included it as the obvious baseline. In a strongly layered graph like the supply chain graph, degree turns out to be only mildly discriminating, because every distributor talks to every fab in its tier whether or not those connections matter for flow. So degree mostly recovers “which big company has many customers,” which we already knew.

Betweenness centrality. The fraction of shortest paths between all node pairs that pass through v:

∑s ≠ v ≠ t

σ_st(v)σ**st where σ_st is the number of shortest s → t paths and σ_st(v) is the number of those that pass through v. This is the “chokepoint” metric: high betweenness means a node sits on many paths that have no good alternative. I deliberately do not weight betweenness by edge capacity, because in NetworkX edge weights are interpreted as path distance, but here a high-capacity edge means flow is easier, not longer. Capacity-weighting would invert the semantics.

Clustering coefficient. For a node v with neighbour set N(v), the local clustering coefficient is the fraction of pairs of neighbours {u, w} ⊆ N(v) for which the edge (u,w) also exists. I projected the graph to undirected before computing it. The global clustering is just the average of C_C(v) over all nodes. Unlike degree and betweenness, clustering doesn't measure a single node's importance. It measures how tightly knit each neighbourhood is, and the literature value to compare against is the Watts-Strogatz small-world expectation [3] of high clustering plus short paths. I revisit the actual value in the results.

Node load (capacity-aware). The three metrics above ignore edge capacities. For a capacity graph the natural criticality measure comes from maximum flow. I added a synthetic source connected to all L₀ raw inputs and to ASML/photoresists (with edge capacities equal to each producer's share), and a synthetic sink fed by all L₆ consumers (again share-weighted). To keep each company's market share as a real bottleneck, I applied standard node-splitting: every real node v is replaced by an internal pair v_in → v_out whose edge capacity equals v's global share. Without this trick a node like TSMC, whose 0.7 share is the binding constraint, would not bottleneck the flow at all, because the sum of its incoming silicon, gas, and equipment edges easily exceeds 0.7.

I then computed the maximum flow from source to sink using the Edmonds-Karp algorithm [7], and defined each node's load as the fraction of that baseline flow that traverses its internal edge:

f(v_in, v_out)F where f is the optimal flow on the split edge and F is the total maximum flow. This roughly answers “how much of the working supply chain is currently passing through this firm?”

Removal scenarios. For a removal set S ⊆ V I reported two numbers. The first is the baseline load share ∑v ∈ S**L(v): how much of the working chain depended on S. The second is the flow drop after deletion, 1 − F(G \ S) / F(G): how much capacity could not be re-routed. The two metrics often disagree, and that disagreement is an interesting part of the discussion.

Random-vs-targeted attack curves. The classic test for scale-free fragility from Albert et al. [2] is to remove k nodes and watch a network-level property degrade. I did this with k = 1, …, 12, tracking remaining max-flow, and drawing nodes from the L₀–L₅ supply-side pool only (removing L₆ consumers would just delete demand endpoints). The targeted curve uses a greedy worst-case ordering: at each step I pick the node whose removal causes the largest additional drop in max-flow. The random curve is the mean over 25 sampled removal orderings, with a min/max envelope across those 25 (max-flow is monotone non-increasing under removal, so any ±σ band would drift above 1 on a heavy-tailed sample distribution). Scale-free-like networks should make the targeted curve fall off a cliff while the random curve degrades gracefully.

Analysis and Scenarios #

The shape of the graph

The 68-node graph has a global clustering coefficient of 0.0015, effectively zero, since each node's neighbours almost never connect to each other. For example, a typical L₄ fab's neighbours are an L₃ equipment vendor on one side and an L₅ packager on the other. Those two neighbours have no reason to do business with each other directly, and in the public data they don't, so the triangle the clustering coefficient counts never appears. The literature small-world prediction of high clustering plus short paths does not apply to a strongly layered, directed acyclic graph like this supply chain.

The graph is drawn with each layer as its own column, sorted within layers so that lines connecting columns cross as little as possible. Five nodes, TSMC at L₄, ASML EUV at L₃, TSMC CoWoS at L₅, JSR at L₂, and NVIDIA at L₆, visibly bulge. Those same names dominate every centrality ranking in the next subsection.

Who carries the chain

Before getting to the load-based picture, the naive degree-centrality ranking is worth glancing at as a baseline. Sorting all 68 nodes by degree gives a top-10 dominated by L₁ distributors (Linde, Air Liquide, Air Products, Iwatani, Taiyo Nippon, Messer) and four fab nodes that all happen to talk to roughly the same number of suppliers and customers (TSMC, Samsung Foundry, SK hynix, and even Intel Foundry, despite Intel's tiny 0.5% share). The fact that Intel Foundry shows up next to TSMC in degree is itself a sign that the metric is not really doing the work we want. Degree alone treats a 0.5%-share customer relationship the same as a 70%-share one, so it mostly tells us which companies have many doors open rather than which ones the chain depends on.

The next figure shows the top ten by betweenness, which is the first metric where capacity-blindness starts paying off. SK hynix tops the list because it is the dominant HBM memory supplier, sitting structurally between every leading-edge fab and every L₅ packaging node. NVIDIA is second on the consumer side. The next bracket of fabs (TSMC, Samsung Foundry, Intel Foundry) tie on betweenness. Below that, the entire L₁ distributor tier (Linde, Air Liquide, Air Products, Iwatani, Taiyo Nippon) shows up at near-identical scores, because each one sits on the same small number of paths from gas producers to fabs and they share the chokepoint role evenly.

The flow-based load metric tells a sharper story. TSMC carries 71.9% of the baseline supply-chain flow: nearly three quarters of everything that flows from raw inputs to consumers in the optimal max-flow assignment passes through TSMC's wafers. ASML EUV and TSMC CoWoS each carry 61.5%, NVIDIA absorbs 62.5% on the consumer end, and SK hynix sits at 28.1%. These are concentration numbers in disguise. In a healthy network you'd expect 5 to 10 firms each carrying 10 to 20% of the flow, not three carrying 60%+.

The obvious chokepoints, then the less obvious one

The obvious test. What does the math say if I just remove the big names? Removing TSMC (left panel of the next figure) confirms the headline: 71.9% of baseline flow used to go through TSMC. Removing all of ASML's lithography lines wipes out 61.5% of baseline load. Removing TSMC and ASML together, or removing all Taiwanese nodes (TSMC, TSMC CoWoS, UMC, GlobalWafers, ASE, and the smaller foundries), pushes the load number above 100%. A total above 100% is not an error. The load L(v) for a single node is the fraction of total flow passing through v, and a single unit of flow that travels super_source → Shin-Etsu → TSMC → TSMC CoWoS → NVIDIA gets counted once for TSMC's load and once again for TSMC CoWoS's load. Adding loads over a set of nodes that lie on the same path in series double-counts the flow along that path. The 133% figure for “All Taiwan” just means that, on average, the typical flow path passes through about 1.33 Taiwanese nodes.

The less-obvious one. The more interesting question is which less obvious nodes show up on closer inspection. To find them I asked the analysis script for the highest-load node that wasn't already a household name (i.e. excluding TSMC, ASML, TSMC CoWoS, NVIDIA, SK hynix), and didn't sit at L₅ or L₆. The answer was JSR Corporation, a Japanese chemical company whose product, extreme-ultraviolet photoresist, is a thin film of liquid spun onto each wafer before exposure. JSR carries 31.2% of baseline flow, roughly half what TSMC carries despite operating at a fraction of TSMC's revenue and brand recognition. It shares the EUV-resist market with two other Japanese firms, Tokyo Ohka Kogyo (7.3% load, also visible in the load figure) and Shin-Etsu's resist arm. Together, these three Japanese suppliers are nearly as load-bearing for the chain as ASML's lithography monopoly is. They get a tiny fraction of the press attention.

Geographic scenarios. Removing every Taiwanese node from the graph reduces the maximum flow by 49%. This is the clean, headline number. Even with Korean memory, American equipment, and Japanese chemicals untouched, the chain physically cannot route around the loss of Taiwanese fabs and packaging. Removing every Japanese node, by contrast, gives 0% flow drop in the model, because for almost every Japanese supplier (Shin-Etsu, JSR, Iwatani, TEL) the graph contains a non-Japanese alternative with non-zero capacity. I argue in the discussion that this 0% drastically understates the real risk.

Random failures versus targeted attacks

The hand-picked scenarios above pick out specific firms or countries. A more general question is: what does the chain look like under any loss of k supply-side nodes? The Albert–Barabási prediction from the background is that scale-free-like networks should weather random failures gracefully and collapse under targeted attacks on the hubs. The next figure plots remaining max-flow as a fraction of baseline against the number of nodes removed; the methodology is in the methodology section.

Look at the targeted ordering itself: TSMC CoWoS, SK hynix, Samsung Pkg, Intel Foveros, Amkor, ASE. Five of the first six greedy attacks land on L₅ advanced-packaging nodes. The only non-packaging entry, SK hynix, is the dominant HBM memory supplier and the input that TSMC CoWoS hands to NVIDIA, so it sits one tier upstream of the squeeze rather than away from it. So what the network is really telling us is that advanced packaging is the chain's single tightest layer, and HBM sits right next to it. The first removal alone drops max-flow to 54%. Adding SK hynix takes it to 26%. By the sixth attack the chain is at 10% of baseline, which is essentially the residual non-AI demand path that flows through mature foundries straight to PC and auto consumers without ever touching the AI-chip packaging route at all. Random failure, by contrast, leaves capacity essentially untouched: the mean random ordering still preserves 79% of baseline after twelve removals, and even the worst-luck random sample only reaches 21%.

It is fair to ask whether the packaging finding is a dataset artifact: the graph contains only five L₅ nodes compared with 14 L₄ fabs and 16 L₀ raw inputs, and removing five out of five of any layer is going to collapse it. The honest answer is no, this is not an artifact. The real-world advanced-packaging universe really does consist of roughly five major players (TSMC CoWoS, Samsung Pkg, Intel Foveros, ASE, Amkor) and that is the entire short list. CoWoS shortages have been the binding constraint on AI-chip availability for the better part of two years now (TSMC's own earnings calls have flagged it as the gating item every quarter since 2023), and the model is reproducing a known fact about industry concentration rather than padding the story with a synthetic bottleneck.

Discussion: Where the Math Is Helpful, Where It Is Misleading #

The most striking thing about the removal-scenario figure is how much the two panels disagree. Removing TSMC reveals 71.9% baseline load but only 0% flow drop. The same is true for ASML, JSR, and even TSMC + ASML together. The network's max-flow value stays at 0.96, because the algorithm finds alternative paths through the smaller foundries, the DUV lithography lines, and the memory-only routes through SK hynix. By the math, the chain re-routes itself perfectly.

By any common-sense reading this is wrong. The smaller foundries cannot scale 30% share to 100% overnight, and without ASML no fab can produce sub-7nm logic at all. The model is right that some capacity exists in alternative paths, but it misses two real-world frictions:

1. AND-dependencies. An NVIDIA chip needs leading-edge logicand HBM memoryand CoWoS packaging. Max-flow models a single commodity. It does not know that flow through TSMC and flow through SK hynix have tocompose , not substitute.
2. Spare capacity is not slack. Edge capacities in the graph are 2024–2025actual market shares. A foundry that holds 5% share is running at ~100% utilisation at that share. It cannot absorb a 70% redirection overnight, even though the math treats its capacity as available. Real spare capacity is closer to a few percent at most leading-edge fabs.

The right way to read the removal-scenario figure is therefore that the load bar is the closer match to real-world dependency, and the flow-drop bar is a lower bound. “Even under the kindest assumptions about substitutability, here is the floor of the damage.” The geographic Taiwan scenario is the one case where both panels agree, and that's because removing every Taiwanese node also removes every realistic substitute, leaving no path for the algorithm to re-route through.

Load and criticality are not the same ranking. The other surprise hiding in the robustness figure is who the greedy attacker does not pick. TSMC has the highest baseline load in the entire network at 71.9%, and yet the worst-case attack opens with TSMC CoWoS instead. The reason is that “load” and “single-node criticality” are measuring different things. Load is the share of the baseline flow that currently traverses a node, so it tracks how much the chain leans on that firm at the moment. Criticality is what fraction of the flow cannot be re-routed if the firm vanishes, so it tracks substitutability. The two converge for nodes whose role no one else can play (TSMC CoWoS at 2.5D packaging, SK hynix at HBM), and they diverge for nodes whose role the rest of the network can absorb on paper (TSMC itself, because Samsung Foundry and the smaller foundries can in principle take over logic production, even though, as the AND-dependency note above explains, in practice they cannot). Load tells you what is important today; criticality tells you what is irreplaceable; both matter.

Sanity check on the share numbers. A reasonable worry is whether these findings depend on the precise market-share estimates, several of which are 2024–2025 figures that will drift over time. I re-ran betweenness 50 times with ±20% uniform noise on every edge capacity, and the top-five rankings did not move. The structural findings come from who connects to whom, not from how big any one edge is.

Policy implications. Read together, the results suggest a narrow but actionable shopping list for “graph-guided redundancy,” and the robustness curve picks the order. The first item is to build alternative advanced-packaging capacity. The targeted-attack experiment says CoWoS-style 2.5D packaging is the network's tightest squeeze, and the rest of the world has not built much of it outside Taiwan and Korea; the alternative packagers we already have (Intel Foveros, ASE, Amkor) are 3–5% of the relevant capacity each. Anything that brings a real non-CoWoS option online at scale buys back a lot more chain capacity per dollar than anything else on this list. After packaging: a non-Taiwanese leading-edge fab so that any path can bypass TSMC, a non-Japanese EUV-photoresist supplier (the JSR/TOK/Shin-Etsu cluster is the chain's quietest single-country dependency), and non-ASML lithography options at scale. None of this is news to the people writing semiconductor industrial policy. What graph theory adds is that these few interventions are nearly the entire policy shopping list. The long tail of distributors, smaller fabs, and minor OSATs either has natural substitutes or contributes a bounded fraction of load. Worry about the packaging line first.

Where the data is missing. The biggest blind spot in the graph is the sub-tier suppliers I collapsed: the chemicals that go into the photoresists, the optics inside the EUV machine (Zeiss), the rare gases inside specific etching steps. If the math says “X is unimportant” but the news says X is vital, my first guess is that the relevant chokepoint is below X in a tier I didn't capture, not that the math is wrong about X.

Conclusion #

A graph-theoretic view of the global semiconductor supply chain recovers, from structure alone, almost every chokepoint that the policy literature has pointed to: TSMC at the foundry tier, ASML at lithography, TSMC CoWoS at advanced packaging, SK hynix at HBM, and a Japanese photoresist cluster (JSR, TOK, Shin-Etsu Chem) that the math labels “surprisingly load-bearing” even though it carries no household recognition. The sharpest finding from the attack experiment is that advanced packaging is the network's single tightest layer: five of the six greedy worst-case attacks land on L₅ packaging nodes, and removing all five plus SK hynix collapses max-flow to 10% of baseline. Three nodes each carry 60–70% of baseline flow. Removing all of Taiwan halves the network's capacity. Random failures of the same number of supply-side nodes leave most of the capacity intact, which is exactly what the scale-free prediction said should happen. The rankings are robust to ±20% noise in the underlying share estimates.

The honest caveat is that single-node removal often shows 0% capacity drop, because plain max-flow does not know about the AND-dependencies that make a finished AI chip require logic and memory and packaging together. The right reading is that the load metric measures dependency (what the network currently uses), and flow drop measures substitutability (what survives, optimistically). They should be reported together.

The deeper question, whether a meaningfully decentralised semiconductor graph is even physically achievable given how thin the talent and capital markets for fabs are, is outside the scope of this analysis. What the analysis does make clear is that advanced packaging is the layer that should be addressed first for a healthier network.

I share more work like this on X, @haddyalchaer.

Acknowledgements #

I am grateful to Professor Shreyas Sundaram, whose course ECE 60270 inspired this project and gave me the tools to carry it out. I am also thankful for his feedback on the initial idea, for reading the final paper, and for encouraging me to publish it.

References #

1. [1] A.-L. Barabási and R. Albert. “Emergence of scaling in random networks.” Science 286(5439):509–512, 1999.
2. [2] R. Albert, H. Jeong, and A.-L. Barabási. “Error and attack tolerance of complex networks.” Nature 406:378–382, 2000.
3. [3] D. Watts and S. Strogatz. “Collective dynamics of small-world networks.” Nature 393:440–442, 1998.
4. [4] Y. Sheffi. The Resilient Enterprise: Overcoming Vulnerability for Competitive Advantage. MIT Press, 2005.
5. [5] J. Goodrich and W. Reinsch. “Mapping the Semiconductor Supply Chain.” CSIS Brief, 2020.
6. [6] European Commission Joint Research Centre. “Supply chain analysis and material demand forecast in strategic technologies and sectors in the EU.” JRC Report, 2022.
7. [7] J. Edmonds and R. Karp. “Theoretical improvements in algorithmic efficiency for network flow problems.” Journal of the ACM 19(2):248–264, 1972.
8. [8] K. Sugiyama, S. Tagawa, and M. Toda. “Methods for visual understanding of hierarchical system structures.” IEEE Trans. Systems, Man, and Cybernetics 11(2):109–125, 1981.

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