Sandisk has taped out the first High Bandwidth Flash memory die. The company put it on a slide at its 2026 Investor Day on August 13, under the header HBF Roadmap, next to what the slide labels an actual die picture. The second half of that slide covers the first HBF inference product samples: coming soon, 2027.
A tapeout is a substantial milestone with any new silicon. It means the design is finished and committed to a mask set, which is the point where an architecture stops being a slide and starts being silicon. It is also several steps short of a product. The wafers have to come back from the fab, the die has to hit its target specs, yield has to climb to something economic, and the die then has to survive stacking into 8-high and 16-high configurations with a working logic die and controller underneath. After that comes thermal and endurance qualification, the accelerator software work to actually address the memory, and customer qualification cycles that run in quarters. Sandisk is telling investors that the first of those steps is done.
What Sandisk Says HBF Delivers #
HBF stacks NAND rather than DRAM and puts it in an HBM-style package next to the accelerator. Per Sandisk’s own HBF fact sheet, the first generation targets 512GB per stack, built from sixteen 256Gb die, at 1.6TB/s of read bandwidth. Sandisk claims that lands at up to 8 to 16 times the capacity of HBM at a similar cost, in a package that closely matches HBM4’s footprint, stack height, and power profile. Because it is NAND, it is non-volatile and spends no power on refresh.
The roadmap on the fact sheet runs further. A second generation targets more than 2TB/s and up to 1TB per stack at 0.8 times the first generation’s power, and a third pushes past 3.2TB/s and up to 1.5TB per stack at 0.64 times the power. The Investor Day deck frames the target workloads plainly: mixture-of-experts LLMs, long context lengths, and large KV caches, with the architecture developed using input from major cloud and AI customers.
The deck also lays out three deployments. HBF can augment HBM, filling some of the stack positions around an xPU while HBM keeps the rest. It can replace HBM stacks outright in a similar footprint. Or it can sit disaggregated, holding decode weights and KV cache while a smaller HBM tier acts as cache. That flexibility matters more than it sounds, because it lets HBF into a socket without requiring an accelerator vendor to abandon HBM.
The Internal Numbers Sandisk Put On Screen #
Sandisk showed an inference token output comparison covering one HBF GPU, four HBF GPUs, and eight HBM GPUs. From it, the company draws two claims, both labeled as based on internal testing. The first is an 8x capex efficiency figure, defined as the minimum configuration required to run the model: one HBF GPU against eight HBM GPUs. The second is a 2x GPU efficiency figure: four HBF GPUs delivering the same token output as eight HBM GPUs. The fact sheet adds a related simulation result: HBF landing within 2.2% of unlimited-capacity HBM when reading pretrained weights for Llama 3.1 405B.
These are vendor numbers on unreleased silicon, and the chart in question carries no axis values for tokens per second. They describe the concept though: if a model fits in memory that is eight to sixteen times larger for the same bandwidth and roughly the same power, you need fewer accelerators to hold it, and the ones you have spend less time waiting.
Where the Timeline Stands #
For planning purposes, two Sandisk statements bracket the schedule. In August 2025, the company said the first HBF samples were targeted for the second half of calendar 2026, with AI inference devices using HBF expected in early 2027. As of the August 2026 Investor Day, the first HBF inference product samples are listed as coming soon in 2027. Schedules for new memory classes firm up as designs become silicon, and first-generation platforms across this cycle have moved to the right as qualification realities set in. The tapeout is the evidence that HBF is progressing; however.
The Ecosystem Piece Is Further Along Than the Silicon #
The standards work is moving faster than the product. On August 3, Sandisk and SK hynix released the first HBF technical specification through the Open Compute Project, six months after the consortium formed, with Google and Tenstorrent among the contributors. We covered that specification and what it defines when it landed. Sandisk also used the Investor Day to name David Patterson, the Berkeley professor emeritus and Google fellow behind RISC, as a new member of the consortium’s advisory group.
SK hynix, which co-authored the spec and showed its own tiered memory pitch at FMS 2026, is the other half of whether this becomes a standard or a single-vendor product. For now, Sandisk has a taped-out die, a spec in the open, and a 2027 date on samples. The next real checkpoint is silicon that measures up, and that will come from a fab report, which hopefully Sandisk talks more about in the near future.