NVIDIA's reported Rosa CPU roadmap points to TSMC A16 back-side power delivery for a 2028 data-center platform, according to TrendForce and Wccftech coverage citing Commercial Times and ICSmart. For ML infrastructure teams, the practical issue is power delivery: moving the power network to the wafer backside can free front-side routing for signals, reduce IR drop, and improve density, but it also raises packaging, carrier-wafer, and process-qualification complexity. TSMC describes A16 Super Power Rail as a high-performance-computing process option, while the Rosa node choice remains reported rather than confirmed by NVIDIA or TSMC. Treat the roadmap details as credible industry reporting, not a vendor commitment.
The Rosa report matters because AI CPU design is increasingly constrained by power delivery, packaging, and platform-level throughput rather than core count alone. If NVIDIA uses TSMC A16 with back-side power delivery, the infrastructure story would be about bring-up risk and supply-chain readiness as much as peak performance.
What happened
TrendForce reported on July 9, 2026 that NVIDIA's next-generation Rosa CPU may use TSMC's 2nm-class process and could adopt the A16 process with Super Power Rail, TSMC's back-side power-delivery technology. TrendForce attributes the node discussion to Commercial Times and cites ICSmart for a 2028 Rosa/Feynman data-center platform target. Wccftech reported the same Rosa/A16 framing, while Tom's Hardware previously described NVIDIA's 2028 data-center roadmap as pairing Rosa CPUs with Feynman GPUs.
Technical context
TSMC's A16 materials describe Super Power Rail as moving power delivery to the wafer backside so front-side routing can be used more heavily for signal interconnects. Wccftech's A16 process coverage cites TSMC guidance of 8-10% speed improvement, 15-20% power reduction at the same speed, and up to 1.10x density versus N2P. Those are process-level figures, not measured Rosa silicon results.
Industry context
Back-side power delivery can improve performance per watt for dense HPC logic, but it also changes manufacturing and packaging dependencies. TrendForce notes that Commercial Times sources expect additional CMP demand and more carrier-wafer exposure if Rosa adopts A16. For AI infrastructure buyers, that means the supply-chain watchlist should include foundry qualification, substrates, thermal validation, and platform timing, not only CPU specifications.
What to watch
The strongest confirmation would be an NVIDIA or TSMC disclosure naming Rosa's process node, followed by platform details for Rigel cores, memory, interconnect, and BlueField integration. Until then, treat 2028, A16 adoption, and 128-plus core chatter as industry-reporting signals that may change before silicon ships.
Key Points #
- 1Rosa A16 reporting is important because power delivery and packaging now shape AI CPU platform economics.
- 2TSMC describes A16 Super Power Rail as freeing front-side routing and improving density, but Rosa silicon is unconfirmed.
- 3Teams should watch foundry qualification, substrates, thermal validation, and official NVIDIA disclosures before assuming 2028 availability.
Scoring Rationale #
The report is notable for ML infrastructure because A16 and back-side power delivery would affect CPU power, packaging, and supply-chain planning for future AI data-center platforms. The node choice and timing remain industry-reported rather than vendor-confirmed, so the score should not move above the notable tier.
Sources #
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