A new chip architecture from IBM can integrate nearly 100 billion transistors on a chip the size of a human fingernail—nearly twice the transistor density of the company’s previous generation of chip technology. The resulting improvement in chip compute performance and energy efficiency comes from what IBM describes as the “world’s first sub-1 nanometer chip technology” for AI data centers.
“It’s not just an incremental step, it’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research and IBM Fellow, in an advance media briefing. He described the new chip technology as “pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.”
It’s worth unpacking what the “world’s first sub-1 nanometer chip technology” means, because it is impractical to build reliably functional chips with transistors and other features smaller than 1 nanometer due to various physical limitations. Instead, IBM is basically claiming that its new “nanostack” architecture can deliver the computing performance improvements that would be expected if a theoretical chip could be built with physical features smaller than 1 nanometer.
Specifically, IBM describes its new chip technology as being built at the 0.7-nanometer node, which it has named the 7 angstrom node because one nanometer consists of 10 angstroms.
But keep in mind that such node numbers have nothing to do with the actual physical dimensions of IBM’s chip features. Older generations of chips developed in the 1970s and 1980s had physical features with dimensions matching the number in the name of their chip technology’s node or process—such as chips made at the 180-nanometer node—but that has not been the case for decades and certainly not for the latest chip generations made with a 3-nanometer or 2-nanometer process.