Credo unveiled plans to create standards for chiplet interconnects to address the AI memory wall.
The San Jose, California-headquartered vendor formed the Lightweight Serial Interconnect (LSI) Workstream within the Open Compute Project (OCP). It plans to contribute its OmniConnect lightweight AXI framer specification to fuel efforts to create an open ecosystem of chip-to-chip interconnects that can plug the growing gap between processor performance and memory access speeds.
“We formed the OCP LSI Workstream to address a clear industry need for innovative interconnect solutions that address the memory wall problem while also enabling a new generation of high-bandwidth and power-optimized modular architectures for AI systems,” Credo VP of Product Vishal Shah explained.
Credo’s OmniConnect interconnect architecture combines a 112-gigabit short-reach chip-to-chip serializer-deserializer (SerDes) with the Arm-developed Advanced eXtensible Interface (AXI) bus protocol. The combination provides high-bandwidth, low-latency connectivity between compute engines and memory, whether on-die or across chiplets.
The first product to make use of Credo’s AXI-over-VSR SerDes bus is its Weaver line, a low-power, double data-rate 5X (LPDDR5X) chiplet capable of providing high memory capacity in a lightweight form factor.
Credo wants to foster an open community around its OmniConnect architecture with third parties to help beat the ongoing high-bandwidth memory shortage. The vendor claimed that AI system designers making use of its proposed architecture could benefit from up to a 25-times increase in memory density and a 5% increase in bandwidth compared to high-bandwidth memory four (HBM4).
“Advancing an open approach to lightweight framing and serial interconnect is critical to enabling flexible chiplet integration, including near-package pluggable configurations, for the next wave of AI inference,” Shah said.
“Credo’s intended contribution of the lightweight AXI framer specification to OCP is an important step toward aligning the industry around AI interconnect architectures that enable interoperability, reduce complexity, and support the high-performance requirements of next-generation AI infrastructure,” Anu Ramamurthy, co-lead for OCP’s Open Chiplet Economy Subproject, added.
Formation of the LSI Workstream is the latest OCP-backed project aimed at boosting interconnectivity for AI infrastructure. In August alone the Open Silicon Photonics for AI Systems initiative launched, which looks to create open specifications for co-packaged optics (CPO), followed by the unveiling of the first standard for high-bandwidth flash, the HBM alternative being spearheaded by Sandisk and SK Hynix. March, meanwhile, saw the creation of the Ethernet-based scale-up networking (ESUN) specification.