Nearly every major Chinese AI hardware vendor at WAIC 2026 showcased a supernode. The components required to build them at scale have not caught up.
At last year’s World Artificial Intelligence Conference in Shanghai, Huawei stood alone. Its CloudMatrix 384, a system binding 384 AI processors into a single compute fabric, was the exhibition’s centerpiece. No domestic competitor displayed anything comparable.
Twelve months later, the field had inverted. At WAIC 2026, nearly every major Chinese chip and server vendor arrived with a competing supernode design. Moore Threads, a domestic GPU company, showed a 256-GPU system built around a single-layer scale-up fabric. Enflame Technology, an AI chip company, partnered with ZTE on a zero-cable orthogonal design. Biren Technology, a Shanghai-based AI chip startup, introduced optical interconnect targeting 1,024 accelerators. Kunlunxin (Baidu’s chip unit), Lenovo, and others brought competing designs. Huawei unveiled its next generation: the Atlas 950 SuperPoD, with 1,024 Ascend processors on display and a design maximum of 8,192.
The concept now carries a published definition. Pengcheng Laboratory, a national computing research facility in Shenzhen, and the Global Computing Alliance published the first white paperspecifying 3 technical requirements for a supernode: memory-semantic access with unified addressing across physical nodes, ultra-low latency, and ultra-high bandwidth. The decisive criterion is whether processors on separate servers can execute load and store operations against each other’s memory, as though they shared the same board.
The competitive unit in China’s AI hardware sector is moving from the chip toward the integrated system. Huatai Securities, a Chinese brokerage, projects the domestic supernode market at Rmb 341.4bn (approximately $50.2bn) by 2028, implying a compound annual growth rate of 194% from 2026.
Why 2026, Not 2025
Two demand-side forces converged this year.
The first is model scale. Moonshot AI, a Beijing-based foundation model company, released Kimi K3 in July with 2.8 trillion parameters. It reportedly requires at least 64 accelerator cards organized as a supernode for deployment. DeepSeek’s V4-Pro pricing page notes that throughput is constrained by compute availability and flags a price reduction once Ascend 950 supernodes ship at scale. As I examined in a previous analysis, the model’s commercial roadmap is explicitly timed to a domestic chip delivery schedule.
The second is a shift in who consumes tokens. AI agents can generate and consume tokens at 100 to 120 per second, several times the 25 to 30 a person reads. A single agent task consumes an estimated 4 times the tokens of a standard conversation, with multi-agent coordination reaching 15 times. That growth raises the value of low-latency, high-bandwidth interconnect inside large clusters, and strengthens the commercial case for supernodes.
The demand case is clear. Whether China’s system-level design lead can hold depends on a harder question: what happens when a supernode’s architecture runs ahead of the components inside it?
Behind the shared label are three different interconnect bets, a component supply chain that has not kept pace with system design, and a utilization problem that better hardware alone will not solve.
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