Cadence's ChipStack claim is not that engineers disappear tomorrow. It is sharper than that: a verification loop that used to consume weeks can now be handed to an agent, and customers are already paying Cadence as if that shift is real.
At Computex 2026 in Taipei on June 1, Cadence unveiled what it called the first fully autonomous virtual engineer for chip design. The system, built with Nvidia's Nemotron models and secured by Nvidia OpenShell, takes a design directive, checks where the project stands, chooses the next step, applies Cadence tools and keeps iterating until the work closes. That is a big claim. It also lands in a part of chipmaking where delays are expensive and patience is thin.
Here's what that looks like in practice. Cadence says ChipStack can run hundreds of dynamic simulations through Xcelium while using Jasper for formal verification. Nvidia's on-demand transcript of Jensen Huang's Computex keynote shows the demo moving through RTL generation, testbench creation, regression testing and debug. According to Cadence, the result is more than 40 times faster RTL validation, cutting a typical five-week verification loop to less than a day. Five weeks to one day. Early-access customers are expected to get the Level 5 capability in the second half of 2026.
The Money Behind the Claim #
You'd expect a claim like that to come with an asterisk. It mostly doesn't, at least not in Cadence's latest numbers. Cadence reported on July 27 that second-quarter revenue reached $1.584 billion, up from $1.275 billion a year earlier. Backlog closed the quarter at a record $8.1 billion. Of that, $4.2 billion is expected to turn into revenue over the next 12 months. Core EDA, the mature business, grew 18%, while IP revenue climbed more than 40% and System Design and Analysis rose 37%. Non-GAAP operating margin expanded to 45.5%, and non-GAAP earnings per share rose to $2.11 from $1.65. The numbers back the pitch.
Cadence also raised its full-year 2026 revenue outlook to $6.26 billion to $6.34 billion, up from the earlier range of $6.125 billion to $6.225 billion. Management tied that lift to AI-driven design demand, not a one-quarter sales spike. You can see why. AI training and inference chips now carry more custom logic and tighter power limits. That leaves more verification work than older designs ever required. Verifying that by hand doesn't scale well. Cadence's bet is that agentic tools are no longer a side feature. They are becoming the workflow.
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The backlog is the important part. A keynote can make any software look clean for 90 seconds. Signed contracts are harder to fake. Customers are not committing billions to Cadence because an agent sounds futuristic. They are doing it because design teams are under pressure to ship more complex chips without adding enough senior verification engineers to match the workload.
Who Still Does the Work #
There is a recursive story sitting underneath all this. You miss it if you only read the earnings print. AI is starting to verify, and in some places design, the chips that power AI models. Huang put the point plainly in his Computex keynote when he said Nvidia has thousands of chip designers and would use vast numbers of Cadence super agents to move faster. That is not a headcount cut announcement. It is a message about getting more done with the engineers they already have.
Frankly, the skeptical read deserves airtime too. A tool vendor will always talk up how much of the design flow its own AI now owns. Cadence is selling the shovel in an AI chip gold rush, so its framing deserves a sceptical read. But the underlying facts are still hard to wave away: Cadence says ChipStack is already in production across multiple chip designs, and its February launch named Altera, Nvidia, Qualcomm and Tenstorrent among early deployments.
Synopsys, Cadence's main rival in electronic design automation, is pushing in the same direction. The Futurum Group noted after Computex that Synopsys demonstrated an autonomous AI engineer using Ansys IcePak to mesh, simulate and optimize GPU cooling inside Nvidia NemoClaw. This isn't happening in a vacuum. The difference is Cadence's framing: not an assistant that speeds up an engineer's existing workflow, but an agent that runs the workflow and lets engineers inspect and step in when needed.
That distinction matters for you if you build, fund or buy silicon-heavy technology. The scarce resource in advanced chip design is not just compute. It is expert engineering time. If Level 5 ChipStack works outside carefully staged demos, the EDA industry's labour model shifts from engineers executing every step to engineers supervising more outcomes at once. That is the wager.
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