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Aisin and Tohoku University Build 16nm AI Chip Using Embedded STT-MRAM to Cut Inference Power

Tohoku University and Aisin announced on November 2, 2026 a jointly developed AI chip that uses embedded STT-MRAM and near-memory computing to eliminate external DRAM and SSDs, cutting energy consumption to one-fiftieth, object detection inference time to one-tenth, and power-on-to-OS boot time by roughly 39 times versus conventional designs. The SoC is manufactured on TSMC's 16nm FinFET process and integrates a 32MB STT-MRAM array, an AI accelerator, two Arm Cortex-A53 CPU cores, and an Arm Mali-G31 GPU. Volume production timing, target vehicle models, wafer pricing and STT-MRAM yield economics on the 16nm baseline, and licensing beyond Aisin's automotive applications remain undisclosed.

by read2 min views4 publishedNov 7, 2026
Aisin and Tohoku University Build 16nm AI Chip Using Embedded STT-MRAM to Cut Inference Power
Image: Asiaai (auto-discovered)

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This story ran in Issue #149, alongside three other stories. Semiconductors & Hardware

What happened

Tohoku University and Aisin have developed an AI chip featuring embedded STT-MRAM that eliminates external DRAM and SSDs through near-memory computing. The architecture accelerates OS boot times by roughly 39 times, cuts object detection inference time to one-tenth, and reduces energy consumption to one-fiftieth compared to conventional designs. Manufactured on TSMC’s 16nm FinFET process, the SoC integrates a 32MB STT-MRAM array, an AI accelerator, two Arm Cortex-A53 CPU cores, and an Arm Mali-G31 GPU.

Key details

  • Tohoku University and Aisin jointly developed a near-memory computing AI chip featuring embedded STT-MRAM on November 2, 2026.
  • The chip is manufactured using TSMC’s 16nm FinFET process and integrates a 32MB STT-MRAM block, an AI accelerator, two Arm Cortex-A53 cores, and an Arm Mali-G31 GPU.
  • The design reduces power-on to OS boot time by approximately 39 times, cuts object detection time to about one-tenth, and lowers energy consumption by a factor of 50.

What remains unclear

  • Volume production schedule and target vehicle models for initial deployment
  • Wafer pricing and yield economics of integrating STT-MRAM into a 16nm FinFET baseline process
  • Plans for commercial licensing beyond Aisin’s proprietary automotive applications

Source: MONOist (ITmedia) · source published November 6, 2026

Japanese industrial firms are aggressively pursuing edge-AI architectures that bypass memory bandwidth bottlenecks without relying on power-hungry external DRAM. This development underscores how traditional automotive suppliers like Aisin are vertically integrating specialized silicon to meet the rigorous latency and thermal constraints of software-defined vehicles.

For the wider picture, see [Japan Semiconductor Ecosystem](https://asiaai.fyi/guides/japan-semiconductor-ecosystem/).

Original source (Japanese)

世界初「STT-MRAMを搭載した16nm AI SoC」が誕生 SDV推進に向けた動きも加速

Published November 6, 2026

This story appeared in AsiaAI.FYI Issue #149. Get AsiaAI.FYI in your inbox — subscribe free.

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