If DAC 2025 was about agentic AI arriving in electronic design, DAC 2026 was about making it work in the reality of silicon‑to‑systems engineering. Across the show floor and executive interviews, three themes dominated: agentic AI as the new automation layer, multi‑physics as the defining bottleneck, and standards as the glue that will make it all interoperable at scale. It was also a year in which EDA veterans started talking seriously about unconventional compute and quantum computing as part of the longer‑term path to keep engineering progress from stalling under its own power and complexity demands.
Before we dive into EE Times’ interviews with executives on the show floor, a quick comment on the temporary new venue for DAC 2026, the chips to systems conference. Long Beach, California, seemed like an unusual venue given that DAC had been held in San Francisco in recent years, close to where many attendees are based. However, as many EDA veterans will recall, DAC moved around in the past, including to Anaheim, New Orleans, Orlando, and Las Vegas. The location was not a deterrent then, as those who wanted to attend did attend, and this year was no different. Next year, DAC moves to San Jose, California.
Sections in this article:
View All Nvidia’s debut at DAC: engineers elevated to system-level rather than tool-levelFocusing on physics models and analog designWally Rhines reflects on one year at Silvaco and agentic AI in EDAIntel on advanced packaging and the need for STCOSynopsys panel: open EDA systems and business models based on token usageStandards: Accellera on functional safety and Intel on PADKsA new class of agentic AI startups designing agentsAchieving quantum compute at scale: the path to wafer-scale integrationEDA is cool again
Nvidia’s debut at DAC: engineers elevated to system-level rather than tool-level
The agentic engineering theme has been bandied around so much in the last 18 months, and this year is no exception. Tim Costa, Nvidia’s VP and GM for industrial engineering and quantum, marked Nvidia’s first appearance at DAC—no doubt convinced that Nvidia needed to support the EDA industry, even if only through speaking engagements, as part of the broader narrative around developing next-generation chips. Costa and other executives drummed home a message that Nvidia loves to tell: a world in which the limit on product development is no longer how many experts you can hire, but how much compute you can throw at a chain of tools orchestrated by long‑running AI agents.
Ravi Subramaniam, chief product management officer at Synopsys, said, “There’s $1.4 trillion spent on engineering. About 10% is digital, 90% is physical. We’re moving toward taking that 90% onto computers.” He said that while Synopsys had been working on the AI aspects since 2017, things have changed dramatically with respect to agentic AI. “At first, it was really driven by chat interactions, small, very short runtime. But now, as the models have evolved, and you can handle much longer running workloads, workflows, it gives the opportunity to start really bringing agents and autonomy together, and that’s what we announced here, which is safe, open, long-running autonomous agents for digital verification.”
These agents Subramaniam described sit on top of existing flows: They run verification, thermal analysis, or implementation tools, interpret log files, decide what to try next, and maintain context over days long runs.
Nvidia’s Costa said this is ultimately about supporting engineers in doing what they wanted to do when they entered engineering: “It is a really exciting time in my mind for the engineers, because instead of being focused on how do I use this one tool, they get to elevate themselves and do what probably brought them into the industry in the first place.” Illustrating this point, he said, “If you’re in [for example] motorsports, you probably have a passion for speed, aerodynamics, but not for how to use one tool in that workflow, and so engineers will elevate to be system-level thinkers, focused on their mission rather than the task of going to specific tools.”
Synopsys’s Subramaniam added that the industry has reached a point where autonomous, Level 4‑style workflow agents (borrowing the automotive industry’s autonomous driving analogy) are moving from demos to early deployments.
Focusing on physics models and analog design
It’s not all about agents, as physics is also a fundamental part of the story. Agentic workflows are only as good as the tools and models they orchestrate, bringing the discussion to everything from thermal analysis to advanced packaging.
Startups such as Vinci are targeting thermal and thermomechanical signoff by training physics foundation models that can replace weeks‑long simulations with automated analysis behind the firewall. “We are the ChatGPT of physics—but deployed in production, behind the firewall, not as a hobby,” said Vinci co-founder and CEO Hardik Kabaria, claiming a speedup of about three orders of magnitude over incumbent flows on real semiconductor packages.
“For a $4 trillion hardware economy, there are only about a million engineers who can really do physics,” he added. “Physics isn’t going away—we want to enable physics intelligence for everyone, everywhere.”
On the analog design side, Indian startup Maieutic Semiconductors, which has raised $6 million in funding, is trying to do something similar for analog design knowledge. The company uses what co-founder Ashish Lachhwani calls a “Socratic” AI that questions engineers and mines internal data to surface the tacit, tribal know‑how embedded in senior designers, particularly around analog expertise. Lachhwani, previously a co-founder of Steradian Semiconductors, which was acquired by Renesas Electronics in 2022, said, “Digital has had automation and shared data for years. In analog, even a five‑transistor circuit can take years to perfect. It’s not about just searching. It’s about knowing what it is and figuring out what to do next—that’s where our added intelligence comes in.”
Wally Rhines reflects on one year at Silvaco and agentic AI in EDA
In a video interview with EE Times, Silvaco CEO and industry veteran Wally Rhines reflected on his first year at the helm of Silvaco. He highlighted how the arrival of agentic workflows is reshaping technology computer-aided design (TCAD), moving the discipline from a specialized, isolated function toward an automated, accessible core layer for the broader engineering ecosystem.
You can watch the video interview below:
He said the real revolution comes with AI: “All of a sudden, the world now has processes that are too complex to develop by running pilot wafers. Now we have to develop virtually, and to do that you need synthetic data to build models. Where does that come from? It comes from physics solvers—for Silvaco, that’s 40 years of building up that capability.”
Rhines said he sees agentic AI as a democratizing force across the foundry-to-design interface. Rather than forcing fab engineers or system architects to become TCAD specialists, autonomous agents can query underlying digital twins via natural language, conduct large-scale design of experiments virtually to diagnose yield anomalies, and optimize process steps in real time.
“Agents are the great equalizers,” Rhines said. “They go look for the best solution. They collect the best data. If I had to be a TCAD expert as a fab engineer, I had to go to the TCAD group. Now I’ve got an agent with an English-language interface that can look it up for me.”
Beyond physics simulation, Rhines pointed to custom semiconductor IP as the second critical leg of Silvaco’s growth story—underscored by its acquisition of Mixel in 2025. As systems engineers demand tailored, low-power interface IP, such as MIPI for AR/VR and automotive sensors, rather than standard off-the-shelf blocks, Silvaco combines zero-defect physical-layer IP with deep, GPU-accelerated TCAD digital twins. Rhines said this gives designers a direct pipeline from atomic-level silicon modeling to full-system realization.
Intel on advanced packaging and the need for STCO
Lalitha Immaneni, VP of semiconductor R&D in the Assembly Test Technology Development organization for Intel, offered a ‘blunt’ assessment: Design teams are still too often “jumping blindly” into complex stacks without adequate multi‑physics guidance or standardized data.
Immaneni cited instances where customer designs with poor copper-density data can force a foundry’s mechanical team to spend three to four weeks cleaning up the database before conducting a three‑to‑four‑week analysis. “That’s not acceptable at this complexity,” she said.
As the executive responsible for the vision and execution of Intel’s centralized package and board flows and tools, as well as EDA ecosystem readiness for Intel’s packaging and board design needs, Immaneni has a broad perspective on the semiconductor packaging industry.
Intel’s answer is system‑technology co‑optimization (STCO), built on its package assembly design kits (PADKs)—the packaging equivalent of a PDK (see Intel bolsters EMIB packaging with EDA tools enablement). PADKs bundle design rules, reference flows, training materials, and Intel‑specific verification scripts for technologies such as EMIB, TSV, and embedded MIM capacitors, co‑certified with HBM memory and IP vendors. “Verification is too late,” she argued. “We should be validating and modeling from the beginning, not discovering warpage after the fact.”
Synopsys panel: open EDA systems and business models based on token usage
A broader silicon-to-systems panel hosted by Synopsys brought together panelists from Synopsys, Qualcomm, and Nvidia. The discussion was chaired and moderated by Prith Banerjee, senior VP of innovation at Synopsys. If you’ve never heard Banerjee speak, he has an authoritative yet humble, professorial style that can politely challenge the status quo. He did just that with two key points on this panel: one related to openness in the EDA ecosystem and the other to the need for EDA business models to change as the industry moves toward agentic AI.
On the first point, Banerjee asked panelists, “In a world where you will have tools from different vendors, do you see in this world an open, agentic framework or not?”
As a user, Paul Penzes, VP of engineering, probably gave the most illustrative response on where the industry stands. Penzes said, “The way I see it is that there are three pillars to the equation. First are the fundamental tools [that the EDA tools vendors] provide. There are the LLMs that other companies provide, and then there is the middle layer where it’s the know-how of engineering tools within companies. With a closed system, you would need all three components at a very high level of expertise, which is actually almost impossible.”
He went on to explain that engineers need to experiment with different tools from different vendors depending on which works best for specific parameters to get to their end goal of pushing PPA (power, performance, and area). He said, “From our user perspective, you can have an agent end to end, but if you have to push PPA, we have to push tools to the very edge. Sometimes we have to take another tool because on that block, the other tool happens to work better. It’s not because there is anything bad.”
Based on this, Penzes said, “We can’t afford a closed system because we will not be able to succeed, especially since the mobile market is extremely competitive. Every millimeter matters, and we need an open system where we can actually do some of those sorts of experiments to get the best chip out there.”
On the evolution of the business model, Banerjee commented, “In this new world of agentic AI, we are actually exploring new business models. The old way of EDA was you buy a piece of software, [with a] perpetual license. Then we move toward lease licenses or timeless licenses. You buy [say] a fusion compiler for $100,000. It’s there for you for a year until you renew it. But in the new world of agentic AI, if these agentic workflows are based on token consumption, the traditional way of ‘you just get an agentic workflow for $100,000’ will not work because depending on your use at your site, you will burn through so many tokens that we’ll have to pay for that, and that is not fair.”
Banerjee continued, “The business model has to go toward a consumption-based model. We are still in early days, and we have not clearly articulated the business model, but [I think] that’s kind of the trajectory.”
Standards: Accellera on functional safety and Intel on PADKs
One of the great things about the semiconductor industry is that it moves full speed ahead with innovation, and startups can get funded to the hilt to go and commercialize their innovative technologies. But without standards, scaling and mass deployment can often be a challenge.
EE Times had two conversations on the standards debate—one with Intel on packaging flows and another with the Accellera Systems Initiative—highlighting how much the next wave of automation depends on machine‑readable, interoperable specifications.
In a conversation with EE Times, Lu Dai, chairman of the Accellera board, discussed the organization’s role as a standards body that can move quickly while still targeting global impact. One focus area is the draft Functional Safety Language (FSL) 1.0 standard, designed to sit under high‑level standards such as ISO 26262.
FSL defines the syntax and semantics of a language and data model for representing and exchanging functional safety intent—focusing on FMEDA (failure modes, effects, and diagnostic analysis)—between tools, teams, and operations across the supply chain, from IP to system level. According to Accellera, by enabling automation, interoperability, and traceability, FSL streamlines the implementation of industry standards such as ISO 26262 and IEC 61508 for safety-critical systems and significantly increases confidence in overall safety compliance.
Dai told EE Times, “ISO 26262 is like a government guideline: ‘You need DFT coverage.’ It doesn’t tell you 80%, 99%, or on which block. [With the proposed FSL standard,] we don’t prescribe 99% coverage. We give you a hook so, if asked, you can say: Here is my requirement, and here is the coverage I actually achieved.”
FSL is expressed as metadata—similar in spirit to unified power format (UPF) and other power formats—so tools can parse and reason about safety requirements and coverage hooks directly. In the background, Accellera is already thinking about how pieces such as FSL, portable stimulus, and mixed‑signal interface standards ultimately feed into the IEEE and possibly ISO ecosystems.
For Intel, PADKs play a similar role at the packaging level, encoding not just rules but system‑level co‑optimization guidelines. This allows customers to mix tools from Cadence, Synopsys, and Siemens without losing the link to Intel’s certified flows. That interoperability, in turn, is essential for any realistic agentic workflow that crosses foundries, IP providers, and tool vendors. A new class of agentic AI startups designing agents
As EE Times reported in ChipAgents CEO on Latest Funding for Agentic AI in EDA, a new class of startups has emerged over the last year or so, built on the idea that the primary design artifact of the future will be agents, rather than RTL.
One such company, founded and led by the former head of Nvidia’s design automation research Mark Ren, suggested we should now be talking about ADA, or agentic design automation, as a new stack that runs in parallel to, and eventually becomes intertwined with, classical EDA.
Ren, founder and CEO of Agentrys, said, “Agentic EDA sounds like a wrapper. We’re talking about rethinking the whole design automation stack—designers won’t design chips; they’ll design agents.” He questioned the value of companies such as design houses relying solely on third‑party agents: “If they only use external agents, what do they really own? The special sauce needs to be their own agents.”
Agentrys’s platform is built in three layers: a secure integration layer that touches every tool and script; a self‑improvement layer that lets agents iteratively refine themselves; and “agent‑native tools” designed for fast, interactive debug and reasoning rather than overnight batch runs. The business model combines on‑premise software with runtime‑metered agent licenses.
A different approach comes from Normal Computing, which pairs EDA tools with ‘unconventional’ compute hardware such as analog matrix engines and stochastic chips. The company is funded in part by ARIA, the U.K. government’s Advanced Research and Invention Agency, often compared with the U.S. Defense Advanced Research Projects Agency (DARPA). “We don’t need to push performance at all costs; our goal is two orders of magnitude efficiency improvement,” said Peter Vigil, DV lead at Normal Computing. He argued that leaning into noise through stochastic computing could help avoid building a new hyperscale data center every time a model grows.
Achieving quantum compute at scale: the path to wafer-scale integration
In the opening keynote at DAC 2026, we heard from John Martinis, a distinguished physicist, 2025 Nobel laureate in physics, and CTO and co-founder of Qolab. His talk provided a glimpse of what might come next for quantum computing.
Martinis walked through the progression from early superconducting tunnel junction experiments—designed to show that a macroscopic electrical circuit could behave as a quantum system—through Google’s 2019 quantum supremacy experiment. The experiment’s cross‑entropy benchmarking fidelity matched error predictions and suggested there was “no hidden physics” blocking the scaleup of quantum.
Looking ahead, Martinis argued that the current “gold chandelier” machines—massive cryogenic stacks with thousands of wires feeding a single chip—have to give way to wafer‑scale integration that looks much more like a modern semiconductor fab flow. “We want to bring the cost of a general‑purpose quantum computer down from tens of billions to about what a regular supercomputer costs,” he said.
EDA is cool again
If there was one theme that summed up where the industry is heading, it came from John Lee, senior VP of EDA software and hardware product management at Synopsys. In the Synopsys executive panel discussion with Nvidia and Qualcomm, he stated that the industry had made EDA “cool again”. That sentiment was palpable, on the show floor, among conference attendees. Lee commented, “I said the industry is cool again. The stakes are so high. The smartest people will be attracted to this industry to help, not to solve the agentic stuff we’re talking about, but also the fundamentals of what drives that. I’m optimistic, and being here at DAC, it’s great to see the startups out here. And on the hardware side, I think there’s going to be a tremendous opportunity, incentive, and innovation to drive that.”
Synopsys’s Subramaniam added, “Essentially, we now have the most comprehensive set of long-running autonomous workflows. And the autonomous piece is really the next piece from the system. Automated, assistive, and now autonomous. We’re at the very beginning of the beginning. We know we’re on the technology hype cycle, and agents are at the peak right now, and so the novelty is there. [The] novelty effect is very high. [The] value effect is what’s got to get proven, and so we expect customers are going to build their own agents.”
The DAC 2026 exhibition and conference certainly felt like it had a buzz around it. The new temporary venue, combined with a raft of new AI agent EDA companies, reflected an industry looking for ways to navigate the complexity of advanced chip designs, advanced packaging, and multiple tools. It’s a whole new world for EDA.
Read also:
[DAC 2025: Agentic AI In EDA Is Just Getting Started, And Chiplets Are All The Rage](https://www.eetimes.com/dac-2025-agentic-ai-in-eda-is-just-getting-started-and-chiplets-are-all-the-rage/)
[DAC 2025: Towards Multi-Agent Systems In EDA](https://www.eetimes.com/dac-2025-towards-multi-agent-systems-in-eda/)
[DAC 2024 Day 3: Wafer-Level Digital Twins, Reusable Chiplets](https://www.eetimes.com/dac-2024-day-3-wafer-level-digital-twins-reusable-chiplets/)
[DAC 2024 Day 2: Wider Context For Systems Design, Plus GenAI EDA Startups](https://www.eetimes.com/dac-2024-day-2-wider-context-for-systems-design-plus-genai-eda-startups/)
[DAC 2024 Day 1: Designing Chiplets and AI with RISC-V](https://www.eetimes.com/dac-2024-day-one-designing-chiplets-and-ai-with-risc-v/)