The 2025 test proved a circuit could recover net energy. Turning it into a useful processor is the harder bet.
By [RuntimeWire Staff](/author/runtimewire-staff)
· Published
Primary source: [MIT Technology Review](https://www.technologyreview.com/2026/09/08/1142079/hannah-earley-computer-chips-recycle-energy/)
Why it matters #
Chipmakers face a power wall as AI demand climbs. Earley's resonator suggests energy recovery can work in CMOS, but Vaire still must prove it inside a useful processor.
Hannah Earley's bet at Vaire Computing moved from a basement whiteboard to a 22-nanometer test chip in 2025, when a resonator she designed recovered more energy than it consumed. The result gave an academic field with more than five decades of theory a piece of working silicon.
The Ice River milestone was reported on May 22, 2025, in coverage from Data Center Dynamics and EE Times, so it is not a new chip launch. A profile published September 8th by MIT Technology Review instead supplies the founder story behind it: a programmer who started around age nine, followed computing down through its layers to the transistor, and came away convinced that waste heat was partly a design decision.
Earley, 31, co-founded Vaire Computing, a reversible-computing semiconductor startup, with Rodolfo Rosini in 2021 after completing a PhD at the University of Cambridge. Vaire's site and Earley's personal website still identify her as CTO and co-founder, although a reported departure post has left her current status unclear. The technical work profiled by MIT Technology Review dates to her years building Vaire's architecture.
From molecular computers to silicon
Earley did not enter Cambridge intending to start a semiconductor company. Her doctoral work began with computation performed through materials such as DNA, under computational biologist Gos Micklem. A few months into the program, Micklem sent her the 1999 doctoral thesis of Michael Frank, a researcher who had spent decades working on reversible computing.
Earley read the thesis, remained skeptical, read it again and eventually redirected her PhD around the physical limits of computation. She developed software for converting ordinary programs into reversible ones and studied how reversible molecular computers would perform when sharing resources and communicating.
The work became sufficiently independent that Micklem told MIT Technology Review he eventually stopped allowing Earley to put his name on her papers because he did not feel able to present them properly himself. Earley finished the degree in 2021. Vaire later hired Frank as a senior scientist, bringing the researcher whose thesis changed her career into the effort to commercialize it.
That commercialization required Earley to cross from mathematical models into chip design. During the winter of 2022, she spent weeks drawing circuitry on a whiteboard in her now-wife's basement apartment in Grinnell, Iowa, while temperatures outside fell to roughly -40 F. The design finally came together after the couple traveled to Las Vegas.
The key component was a resonator, which Earley describes as a microscopic pendulum. It stores electrical energy and sends it back through a circuit instead of allowing all of that energy to dissipate as heat.
Computing without throwing away the route
Conventional digital logic discards intermediate information while reducing inputs to an output. That erasure has a physical cost: electrical energy leaves the circuit as heat. Reversible computing retains enough information to reconstruct earlier states, allowing an operation to be run backward after its result is no longer needed.
The practical system needs two pieces. Reversible logic preserves the route through a calculation. A resonator recovers electrical energy from the circuit and feeds it into subsequent operations. Earley's design uses voltage waveforms that rise and fall gradually, reducing the energy dissipated when transistors switch.
Vaire chose conventional CMOS manufacturing because changing the logic, software model and fabrication technology at once would make an already difficult commercialization effort harder. Its first test chip, Ice River, was fabricated in 22-nanometer CMOS.
The reported measurements require careful boundaries. Data Center Dynamics reported that Ice River's resonator recovered about 50% of its energy on average. Vaire acknowledged that figure applied to the resonator and excluded significant additional overhead elsewhere in a complete system.
EE Times later reported an energy-recovery factor of 1.77 for a capacitor-array test structure and 1.41 for a shift register, both measured against conventionally driven circuits. A result above 1 met Vaire's threshold for showing net recovery in the experiment.
Those are test-structure results, not benchmarks from a production CPU or AI accelerator. According to the same EE Times account, Ice River ran at a 500 MHz data frequency and much of its design was completed semi-manually because little design automation was available for Vaire's architecture. Speed also carries an efficiency trade-off: slower switching can preserve more energy, while commercially useful processors need adequate throughput.
The next demonstration has to look like a product
Vaire still has to integrate its resonator, reversible logic, energy distribution and conventional interfaces into a processor that customers can use with existing software. EE Times reported that Vaire expects existing software to be converted into reversible form rather than written from scratch, with the conversion handled inside the hardware.
The initial target is AI and other workloads that can perform many operations in parallel. Vaire has considered selling its own chips, licensing the underlying intellectual property, and providing custom or co-designed silicon. Each route asks customers to accept architecture risk in return for lower power consumption and heat.
The market pressure is real even if Vaire's answer remains early. The US Department of Energy reported that data centers consumed 176 terawatt-hours of electricity in 2023, or 4.4% of national electricity use, and forecast that consumption could rise to as much as 580 terawatt-hours by 2028. Power availability has become a constraint on where operators can build and expand AI infrastructure.
Vaire's financing has arrived in layers. A $4 million seed round announced in July 2024 was led by 7percent Ventures and angel investor Jude Gomila, with Seedcamp, Clim8 Ventures, Tom Knight and Jared Kopf among the participants named at the time. An Energetik Ventures portfolio update described Vaire's July 2024 funding as $4.5 million. MIT Technology Review now reports that Vaire has raised more than $12 million.
That capital has funded an early technical demonstration, rather than proof of a business. Electronic-design-automation researcher Igor Markov told MIT Technology Review that Vaire would need increasingly realistic demonstrations to attract the industry support required for commercialization.
Earley took a field that had redirected her doctoral research, designed the energy-storage component it lacked and helped put it on a foundry-made chip. A useful processor will require Vaire to repeat that jump across every layer of the computing stack, from circuit tooling to software compatibility. Earley told MIT Technology Review that her ambition was to rethink every part of how computers are built. Ice River established where that work could start.