AI factories are interconnected systems where fleet economics depend on how efficiently the entire stack converts power and capital into completed agent tasks. While GPUs run the models, CPUs handle orchestration, tool execution, and sandboxed computation. Unlike conventional computing with stable runtime profiles, agentic workloads are unpredictable and highly variable. Based on telemetry from 163,594 agentic sessions, over 97% of sessions showed unique trajectory profiles (Figure 1). This variability makes it impractical to right-size a fleet using multiple specialized CPU design points.
Production telemetry also reveals how these diverse trajectories unfold: across sessions, execution follows a long sequential chain of reasoning interspersed with sporadic bursts of parallel work. This real-world data shows that the dominant sequential path is strictly latency-bound—governing overall session completion time—while transient fan-out demands a combination of available thread concurrency and low-latency per-thread execution.
Rather than fragmenting a fleet by planning around isolated tool-calling scenarios, AI factories need a single, balanced CPU design point. The NVIDIA Vera CPU is architected for this balance—delivering top per-core performance on typical agentic workloads to accelerate the critical path while absorbing intermittent fan-out bursts. The following sections examine the telemetry behind these agent trajectories and show how the Vera CPU’s balanced architecture optimizes real-world fleet economics.
Optimizing along the critical path of agentic trajectories #
The shape of an agentic trajectory is defined by its length and width (Figure 2).
Length: How many reasoning steps, tool calls, retries, and sub-tasks are required before the agent resolves a turn.Width: How much work fans out at each stage—concurrent tool calls, retrieval operations, sandboxes, or sub-agents.
A session can have substantial width and still spend most of its wall-clock time waiting on the sequential chain, because parallel bursts are transient while the underlying dependency chain persists throughout the run. Even during wide fan-outs, per-thread latency remains critical. The main agent frequently idles until those parallel tasks complete before advancing to the next step. A CPU fleet must optimize for the full trajectory: providing enough concurrency to absorb fan-out bursts alongside the strong per-thread performance needed to accelerate the sequential path that ultimately determines end-to-end completion time.
This is why the relevant optimization target for an agentic CPU fleet is the total number of completed user sessions, not raw core count. High-core-count systems might appear efficient on paper, but they often force a trade-off. To hit core density targets, they sacrifice the single-thread performance required to minimize latency on the agent’s critical path.
Agentic workflows suffer when forced to run these sequential, latency-sensitive tasks on lower-performance cores, or when they encounter high synchronization overhead across massively parallel, heterogeneous clusters. A balanced CPU for agent workloads must pair enough cores to absorb concurrent tool execution and sub-agent fan-out with strong single-thread performance that accelerates the sequential steps that dominate total agent latency.
What real agent sessions look like
This can be tested against real agent telemetry. In the real-world Claude Code session shown in Figure 3, the main agent advances through a long sequential trajectory for most of the 33-minute run.
The telemetry shows both sides of the agentic workload shape: meaningful fan-out and a long dependency chain. Sub-agent activity creates bursts of parallel work that must be served quickly, but the full user turn still advances through an ordered main trajectory in which each step unlocks the next. The CPU fleet therefore needs enough concurrency to absorb fan-out bursts without delay, while also sustaining strong per-thread performance on the latency-sensitive path that determines end-to-end completion time.
At any given moment, a CPU can effectively “turn off” cores to temporarily boost single-threaded performance. This can leave 8 GB per core unused and impose a significant memory TCO penalty (Figure 4). A well-balanced CPU design optimizes for the entire workload trajectory rather than any single phase in isolation. By combining strong per-thread responsiveness with meaningful concurrency, ample memory bandwidth, and efficient power use, this approach maximizes completed user turns while using CPU cores, DRAM, GPU HBM, and the broader memory hierarchy efficiently.
How Vera CPUs deliver this balance #
The Vera CPU is built for this operating point, with NVIDIA Olympus cores designed to sustain strong per-thread performance while the full CPU is active. The wide front end, advanced branch prediction, deep out-of-order execution, and high-bandwidth memory subsystem help each core maintain forward progress across large code footprints, branch-heavy control flow, dynamic runtimes, and dependency-heavy execution. The Claude Code data above shows that agentic workloads need this same balance: concurrency to absorb fan-out, and per-thread speed to keep the dominant sequential path moving.
The estimated SPEC CPU® 2026 results in Figure 5 put that design point to the test. Highlighting Vera CPU’s loaded per-core performance across typical agentic workloads, including compiler, static analysis, and Python benchmarks—and showing how Olympus handles concurrency without sacrificing the performance needed on the agent critical path—NVIDIA Vera CPU delivers up to 1.5x the agentic performance of the latest competition.
An optimal agentic fleet just needs a single CPU design point #
Vera provides a more efficient CPU foundation for agentic AI fleets because it is built for the full range of real agent trajectories. Strong single-thread performance at full socket load keeps the latency-sensitive sequential path moving, while high concurrency across cores and ample memory bandwidth absorb intermittent tool-call and sub-agent fan-out. Vera CPU’s low-latency monolithic architecture further reduces topology-driven stalls and variability across these phases.
This balanced design helps avoid stranded resources: cores remain productive during both sequential work and parallel bursts, and the memory attached to those cores is used effectively rather than remaining tied to underutilized compute. It also reduces the need to divide the fleet among multiple specialized CPU design points to accommodate unpredictable tool-calling patterns.
The result is a CPU platform that converts compute, memory bandwidth, and power into more completed agent turns—improving AI factory output and fleet economics at scale.
To learn more about the NVIDIA Vera CPU architecture and performance, refer to the NVIDIA Vera CPU Whitepaper.
NVIDIA Vera SPEC CPU® 2026 results measured internally in July 2026. Refer to this NVIDIA Vera CPU Whitepaper for details on performance measurements and configuration. AMD Venice results are based on link. Individual workload performance for Venice was estimated based on SPECrate®2026_int_base score 2070 with components normalized based on internal Turin measurements. Results may vary.
SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation (www.spec.org).
Acknowledgements #
This work was made possible by the expertise and insights of Ivan Goldwasser, Diana Aung, Hannah Coutand, Ian Finder, Benjamin Klieger, Arnav Jaiswal, Dylan Mitic, and many others.