Korea’s ET News reports Samsung has built a 900-layer 3D NAND die by stacking two 450-layer strings together.
The mainstream NAND suppliers are building 192-layer (Solidigm) to 321-layer (SK Hynix) 3D-NAND chips, generally by stacking two layers together. Samsung announced its 400-layer tenth generation V-NAND technology in February last year and intends it to enter mass-production this year. Now it has gone one better with this 900-layer research development.
The research device’s cells function as they should, reading and writing data. Samsung has said it has controlled NAND wafer warpage, due to the thicker NAND stacks, with a so-called Upper Chuck design and a new overlay correction technology. An Upper Chuck holds the wafer from above and must keep the wafer flat and stable during the semiconductor manufacturing process. The overlay correction technology corrects microscopic misalignment issues. Samsung also improved its bitline and wordline structures to reduce electricity consumption and die size.
The ET News report has a diagram comparing 3D-NAND stacking technologies used by Samsung, SK Hynix and China’s YMTC;
We translated it and it shows Samsung's technology distance from SK Hynix and YMTC.;
We also updated our 3D NAND layer cake diagram to reflect Samsung’s 900-layer technology;
It shows that Samsung is a long way ahead of its competitors, with a near 3x layer count increase. This means it could produce higher capacity NAND dies, meaning fewer chips needed in an SSD at any particular capacity level, lowering costs and size, or providing higher-capacity SSDs.
It will also spur competing suppliers to update their NAND layering technologies to match Samsung.