GaAs VCSELs at 200G/lane, unconstrained supply vs. indium phosphide, the 8×200 / 16×100 / 32×50 flavors, WIN Semiconductors, the roadmap to 12.8T, and more
Austin talks with Al Yuen, CEO of PicoJool, about why a 25-year-old technology is the pragmatic answer for scaling up optical interconnects. Al makes the case for GaAs VCSELs over InP single-mode solutions, explains why the VCSEL supply is “unconstrained”, and walks through PicoJool’s newly announced 200-gigabit-per-lane device and its path to 12.8T.
Things we cover:
Inventing the active optical cable with Mellanox
Why hyperscale AI’s error-free requirement changed the game
GaAs (unconstrained) vs. InP (substrate-constrained) The three 1.6T flavors: 8×200, 16×100 LPO, 32×50 NRZ The roadmap to 3.2T and 12.8T via bi-di and 2-D arrays
The fabless model and WIN Semiconductors capacity
This podcast is lightly edited for clarity.
From HP Labs to the First 10 Gigabit Ethernet
Austin: Hello everyone. Today we have a special guest, Al Yuen, CEO of PicoJool. PicoJool is an optical connectivity company and we’ll get into all the interesting details. But first I wanted to introduce you guys to Al. So Al, tell us about you and your background — I know you’ve been in the industry for a long time.
Al: Yes. So after grad school at UC Santa Barbara — where a lot of the photonics folks have originated — I went into HP, HP Labs, where we focused on photonics research. And then around ‘99 I left HP and started my first company, called Alvesta, and we created the world’s first 10 gigabit Ethernet. At the time, 10 gigabit — which is 10 billion bits per second — we were actually trying to figure out applications, how people would use this in ‘99. We would make up things like, people will want to stream video someday in all the rooms in their house. But today, of course, we’re doing 1600 gigabit, or 1.6 terabits. So since then I’ve gone to various companies. I ran a division for Coherent, then started some other solar and clean-tech companies, and finally ended up at Lumentum in my last gig. And about two years ago, through Playground Global — which is our funder — we started PicoJool. So far so good on what we’re doing, which is basically in the interconnect space, and we’ll talk more about that today.
Austin: Awesome. Wow, what a great background. I love that you guys invented early 10 gigabit Ethernet and then had to create ideas to sell people — to convince people that yes, this is useful, people will want to use it. That’s awesome. Now, remind me — you also helped invent the active optical cable. Is that right?
Al: Sure. Very interesting story. Back in Alvesta, my first startup — another small startup at the time called Mellanox, which of course now is inside Nvidia and created this whole hyperscale and the whole InfiniBand ecosystem — they approached us. They had these very bulky copper cables, even back then, 25 years ago. They said, the copper cables are very bulky, they could only reach tens of meters — now it’s even shorter. We’d like an optical option, but we don’t really want to commit to a full optical solution. So could you put the optics inside the connector? And we said, why not? So we took that same transceiver that’s typically on a board and literally embedded it right into the connector. Then we thought, well, that’s not very efficient and clean — so we embedded the whole thing inside; the optics went inside the connector. And this is the world’s first demo of an active optical cable, meaning electrical to electrical: electrical comes in, electrical goes out, but inside there’s the electrical-to-optical transition. Electrons come in, photons carry the information, and electrons go back out at point B. So that’s how the whole active optical cable concept came through Mellanox. And since then, for the last 25 years, the AOC has been the standard workhorse in many, many data centers.
The Engineer’s Mindset and Why Optics Must Exit the Rack
Austin: Amazing. So having invented that and then watched it become widely adopted — produced in the millions of cables — how has that impacted the way you think about what’s possible as an entrepreneur in this space?
Al: I like to think of ourselves more as engineers. There’s a difference between scientists or researchers — what people call R&D — and engineering, or product development. I always tell people I’m more of an engineer. Engineers solve problems and want to create products that meet specifications. If you need a Prius, you certainly don’t design a Ferrari — that’s overkill. The product fits the need: spec, cost, reliability, and in our case reach, or amount of power. So what we do is really look at solving the specific problem. Today, copper has shrunk to about 3 to 4 meters of reach at 200 gigabits per second per lane. And therefore they can’t get the information off each rack. Racks and racks of GPUs, CPUs — lots of compute power — and these racks are getting very hot because they’re packing more and more GPUs per rack, because they can’t exit the rack. To exit the rack, you need an optical solution. There are many technologies, and VCSEL-based active optical cables are one of them — that’s what we’re focused on. Low cost, highly reliable — going way back to our roots, replacing a copper cable with an active optical cable. So the problem really hasn’t changed; it’s just that the speed and aggregate bandwidth is now 1600 times more than the old 1 gigabit Ethernet. It’s exciting. It’s been a long journey, but we’re still at it, and we see a long future for VCSEL-based technology going forward.
Austin: Nice. So you have this history of thinking like an engineer — what is the problem right ahead of us in the industry? Not “we need to invent new physics,” but how can we be thoughtful about it. Same cable form factor in the AOC case, electrons in, electrons out, but we could use optics here — could we put the transceiver on the end of the cable? Thinking very pragmatically. And now, fast forward 25 years, in 2024 you started PicoJool. It sounds like you’re tackling the problem again of communicating lots of information — this time GPUs talking to each other, rack to rack, where it’s such high bandwidth that copper is shrinking to 3 meters or so. So you’re again thinking about how to use active optical cables, but this time with VCSELs. So tell us — why VCSELs, and what about the problem made you want to start PicoJool and actually get in the game?
Why VCSELs — 25 Years of Shipping in the Millions
Al: Great question. VCSELs, for one thing, have been around since ‘96 — a technology that’s been in product, in the field, in data centers since 1996, starting with the first gigabit Ethernet. I’m more of a historian today: here’s a 1 gigabit Ethernet that HP created, and at the time Honeywell — very early companies that did 1 gigabit. And from 1 gigabit all the way to today — 1600 gigabit, what they call 1.6 terabits — it’s all been VCSEL-based. The practicality of these solutions has to meet capacity, demand, cost — all of it. If you’re trying to get into a hyperscaler today, you need to meet the whole checklist. You can’t say, I meet everything but it’s three times the cost of your target; or everything’s great but I can’t get the reach. They want all of it. And right now the only thing that meets it is copper — mainly driven by cost. Cost for copper is very minimal. Even active copper, where you have some signal integrity and signal processing built in, like an AEC — active electrical cable — the cost is still quite minimal compared to more elegant, longer-reach technologies.
Now, what’s important in a data center: when you say “fiber optic communication,” everybody hears it and goes, oh, isn’t that the over-the-ocean stuff, the transatlantic subsea cables? Absolutely — there are many flavors of optical communication; it’s a very big umbrella. What we’re talking about today for data centers is a very short reach — today they call it scale-up. It’s basically a row, typically 25 to 30 meters, or in English terms 75 feet. Very short — within your house, from one end to the other, or potentially even shorter. And in that short reach, the shorter the reach, typically the higher the volume. In the data center you’re connecting all these GPUs, CPUs, and ASICs together — millions of interconnections, miles of fiber inside a data center that may be a football-field length. But when you leave that data center and go between cities, buildings, countries, you have fewer fibers but need longer distance. So back to the data center: you have to have millions-per-month capacity to meet the volume demand.
That’s one of the boxes — you’ve got to check off all the boxes. If you demonstrate one or two racks, or go to a show and demonstrate just the technology — technology, science, R&D show the capability — that’s a demonstration. But to ship in volume, millions per month, you need this whole ecosystem: the connector, the transceiver, the sockets — everything has to be millions per month. And any one of those bill-of-material parts, if it’s missing, then you can’t ship in millions per month. That’s what’s happening with a lot of these new technologies that are fantastic from a demonstration and capability standpoint going forward. But VCSEL’s domination is that for the last 25 years we’ve been shipping in the millions per month. So there’s no invention of a technology, capacity, or foundries needed — we already have that. So we design the latest VCSEL — today it’s 200 gigabit, which we just announced — put it into the whole ecosystem, they package it together, and voila, we can build millions per month without waiting for machines, or even buildings, to be built up, then new machines, then new processes. All of that has existed for the last 25 years to service this short-reach data center application.
Austin: Okay, let me reflect it back to you. The problem you’re solving is scale-up with optical interconnects. But the key insight — with your pragmatic hat on — is: how can we use technology and a supply chain that already exists and can already ship millions of cables, components, and parts per month? That’s one reason VCSELs are so attractive — they’re not a new technology, the supply chain is not new. So even though we hear about all these other interesting things — the Broadcoms, Coherents, Lumentums; silicon photonics, EMLs, micro-LEDs — you’re saying, hey, don’t rule out VCSELs. Even though they’re not new, there are advantages. But if VCSELs have been around so long, why aren’t other folks trying to take them to 200 gig per lane, times eight lanes, 1.6T and beyond?
The Hyperscale Shift to Error-Free
Al: Yeah, like you said, there are multiple technologies — silicon photonics, EML, even micro-LEDs — all vying for this 200 gigabit electrical signal coming in. From the ASIC, GPU, or CPU you have 200G per lane of electrical signal. When you go to the electrical-to-photonic (E-to-O) transition, it can go to different lanes through a different IC that may be a gearbox. You don’t necessarily have to run at 200G straight through — which we can — and that’s the most elegant: straight through without an intermediary gearbox saves power, cost, and latency. So 200 gigabit would be ideal.
But what’s changed in hyperscale is different from Ethernet. Ethernet information is sent in packets. Whatever information — “where should I go in Italy, I’m going on vacation” — gets divided up by your search engine, sent in packets, and comes back to you. We’re not very cognizant if there’s an error drop or some delay, because those are in the hundreds of nanoseconds or milliseconds — to us it’s a thousandth of a second, we don’t notice. But for hyperscale systems, which are literally thousands of GPUs acting as one brain — one supercomputer, one high-performance cluster — that latency is super critical, because the GPU notices anything in the tens or hundreds of nanoseconds. So the typical Ethernet bit error rate needs to drop from 10⁻⁶ to below 10⁻¹⁰, what we call error-free, because any errors slow down the whole training and inference — all the AI infrastructure. That’s changed, and it’s allowed these higher-cost single-mode solutions — single-mode being longer distance, longer reach, very high performance — to come into the data center and hyperscale systems, because of this requirement for very low bit error rate. And now VCSELs have to raise the bar from 10⁻⁶ (typical Ethernet the last 25 years) to 10⁻¹⁰, 10⁻¹². And we’ve done that — we’ve pushed our VCSELs to 200 gigabit, and even used at 100 or 50 gigabit NRZ you can leverage that to very low bit error rate. So the answer is: things changed for hyperscalers to require error-free, and that’s allowed these high-end single-mode solutions to compete directly with VCSELs, because of that additional spec that’s new to hyperscale AI systems.
Austin: Okay. So because the capacity for sustaining errors is much lower — we don’t want all these GPUs just waiting — that changes the game from the cloud/SaaS days to now, when everything’s acting as one big computer. So the bit error rate has to be much lower. And VCSELs, which are short reach, have to come down to meet that; or, what you’re saying is, these other technologies that are longer reach and higher power were already closer to the necessary bit error rate, so people say, why don’t we bring those into short reach? But surely that has power and cost tradeoffs — taking something that talks at low error rate over a long distance and trying to bring it in. So you guys must be taking a different tack: no, no, let’s just make VCSELs error-free. And presumably that’s a cost or power tradeoff you’d rather make — or is it back to the manufacturing supply chain capacity?
One Pizza Oven vs. 5,000 Pizzas — The Capacity Argument
Al: Yeah, it’s again a complicated matrix of items you have to check off. Those shipping silicon photonics and EML for long reach — or DFBs — single-mode, high-performance devices, have been around a similar time, 25 years. They’ve been used for long reach because of that super-high performance, very few fibers, and what we call WDM — wavelength division multiplexing. Fibers are very expensive when you’re going hundreds of kilometers, so you want to use very few fibers but pass more information through more wavelengths, more colors, in that same fiber. For short reach — tens of meters — you’re not as locked into the cost of the fiber; it comes down, because you’re only 10 meters versus 10 kilometers. So the volume supply chain of the high-performance, low-bit-rate device would seem a natural fit: hyperscalers want low bit rate, let’s go with the Ferrari — the super-high-speed, high-performance single mode. But those players have been used to building in maybe 100K — 100,000 — volumes, because you don’t need as many between cities and countries. And all of a sudden they come into the data center. Even though their performance is excellent, the cost is a little higher because of the single-mode packaging. And the infrastructure to build millions per month is 10, 20, 50× what exists. That’s brick and mortar. It’s like: I only have one pizza oven, and I’ve been used to a small clientele — maybe 20 an hour. Someone comes in and says, I’d like to order 5,000 pizzas, and I need them in an hour. You’re going, I need 100 pizza ovens. That’s the exact same problem the high-performance single-mode long-reach players are coming into. Silicon photonics, EML — excellent technology, very good bit rate — but the infrastructure needs to be built up. That’s what you’re seeing: a lot of announcements with people holding shovels, saying we’re investing in the next supply chain, the buildings. That’s great — bringing more manufacturing to the world, and back to the US, all great for the industry. But VCSELs have been around for 25 years and shipping in the millions. So we’re not building, we’re not putting shovel to ground — we’re just changing the actual VCSEL.
We’re just changing the actual VCSEL performance — the chip — and leveraging the existing infrastructure. And so for VCSEL capacity, we call it unconstrained. Constrained means they’re sold out: we’re sold out through next year; if you’re going to place an order, it’s going to be an eight-month, 18-month lead time — a year and a half from now we can get it to you. For us, unconstrained just means we have a certain lead time that’s limited only by our cycle time of building through the factory. A VCSEL run and then a packaging run may be four, eight, twelve weeks — but that’s limited just by the fact that we have to build it and ship it, not by the constraint of the supply and ecosystem of machines, or pizza ovens. We have plenty of pizza ovens: place the order, and we’ll get you your order in the cycle time we commit to.
Austin: Gotcha. Okay, that’s very interesting, and a great competitive advantage for you. So on the constrained side — is that what listeners hear about when they hear about indium phosphide being a bottleneck? Where in the supply chain is it constrained? And for you, what’s different about VCSELs that makes them unconstrained?
InP vs. GaAs and the Fabless Split
Al: Yeah. So a lot of silicon photonics and EMLs are based on this material, indium phosphide. For VCSELs, our technology has always been gallium arsenide. For the listeners it may be, okay, one III-V compound versus another — what’s the difference? Indium phosphide is material-constrained from the very beginning. You can’t even get a base substrate — even before you process it, just the substrates for indium phosphide are limited, before you get it made into a product, whether that’s EML, silicon photonics, or VCSELs. The indium phosphide bare material is already limited. Gallium arsenide: unconstrained. So we start with that. And then you go through the fabs — fabrication depends on foundries, usually very large companies. Companies like PicoJool and others don’t own large clean-room factories. We design the individual VCSEL chip device, and then we use foundries to manufacture it. Those foundries are available — but they can’t get enough indium phosphide starting material. Now, after that, once you get to the chip level — you dice it up, okay, great, I’ve got the laser, I’m ready to go — to get from the chip to a pluggable device, an actual optical engine, there’s a ton of stuff that happens. You’ve got laser drivers, you’ve got boards, and for single mode you have to have all the machines that align that silicon photonics or EML to a very, very small-core single-mode fiber. Those machines have to be readily available. VCSELs, again, have that millions-per-month volume infrastructure — it doesn’t need to be built up. So from the very beginning: indium phosphide material constraint, then you have to build it into lasers, then finally package it into transceivers — and all along that supply chain, it’s not used to building millions per month. All of that has to be built up: hardware, alignment machines, testers. VCSELs have all of that infrastructure existing already.
Austin: I see — yeah, that makes a ton of sense. And I love your props, by the way — I liked the little VCSEL you held up. So tell us more: what are we looking at, and walk us through exactly what you design, and where it gets handed off, built, and packaged — where your responsibilities end.
The VCSEL Tree of Knowledge and the Handoff to WIN
Al: Yeah — so background is super important here. There’s what we call a tree of knowledge of VCSELs. You have this line from Honeywell through Finisar, and Finisar goes into II-VI, which goes into Coherent — so there’s the Coherent line. Then for us, obviously, HP went into Avago, went into Broadcom — the HP–Broadcom line. And finally there’s Picolight and E2O — I’m throwing in some old names from 25, 30 years ago — which go into JDSU, another big name from the dot-com time, and JDSU spins off Lumentum and Viavi. We’re from the Lumentum arm. All three of these major arms have a lot of VCSEL knowledge — and the strength of PicoJool is that we’ve tapped into designers from all three branches. Imagine all that know-how — again, not patented; know-how, recipes. I use this example: you can hand three different chefs a recipe for a soufflé and you’ll most likely get three different soufflés, because it’s really difficult to get a perfect one. It’s not just crack the eggs, beat the eggs. Same thing in the VCSEL.
So to answer your question — what do we do? We take all that know-how and design the epi layers. All these little lines you see — these are epi layers designing this vertical cavity. It’s not edge-emitting, where the light comes out of the edge of a flat chip; VCSELs are vertical-cavity, surface-emitting — the light comes out of the surface. We design the internal cavity of the laser, all the dopings, all the process. After we design, we hand it to an epi foundry that grows the material and gives us back an unprocessed epi wafer. We’ve been working with WIN Semiconductors in Taiwan — that’s our foundry. Once the epi wafer is ready, we hand it to WIN, they run it through their clean-room process, and they make the final VCSEL device. And here’s another beauty of VCSELs versus an edge emitter: at the wafer level you can start testing and probing each one — 100% tested, what they call known good die — before you have to singulate and dice it into arrays. That advantage is huge, because the more work you add before you yield the device, the more value you lose downstream. You always want to yield upstream. Wafer-level testing for VCSELs is a real advantage versus edge-emitting technologies.
And WIN is only the wafer processing. The wafer comes out and is diced into individual VCSELs, and we work with our partners to build those into either active optical cables or transceivers. That’s another foundry, if you will, but a packaging company. That said — companies like TSMC are now going into co-packaging: after they make their silicon wafer, they’ll package the optics directly on top of it. There’s a whole emerging field called CPO, where the traditional wafer-processing foundries are stacking technologies together — 3-D wafer-level packaging. For us: we only do the wafer at WIN, and then that WIN VCSEL goes to our module-integrator partners, who build it up into the active optical cables or transceivers.
Austin: Gotcha, that’s helpful. So take us back to your roadmap. I know you mentioned a 50G version, 100G, 200G — and a recent launch. Tell us more about your roadmap, what you launched, what you announced.
200G/Lane and the Three Flavors of 1.6T
Al: As I mentioned early on, 200 gigabit per lane is the benchmark — the bar you have to clear. EMLs and silicon photonics have all done that, and now VCSELs have reached it. PicoJool just announced our 200 gigabit; we’ll start sampling next quarter. That’s for a very simple transceiver where you have eight channels of 200 gigabit coming in — the aggregate bandwidth of 8×200 is 1600 gigabit, or 1.6 terabits.
So that’s the standard ramping today. There are 800 gigabit transceivers as well, that’s also shipping — that’s 8×100. And the next generation, today’s generation, is 8×200 — the 200 gigabit VCSEL we announced. But there are many flavors of that because of the specification. Aggregate bandwidth 1.6T — check. But there are different ways to get there if you want very low power or very low bit error rate.
Running 200G, I liken it to a Ferrari — it can give you 200 miles per hour, but it’s very high-end, relatively expensive, because you need certain signal integrity and signal processing. So now I say, I want very low cost, low power, but I still want low bit error rate. And what people have done is: let’s slow it down. Let’s use the 200G-performance VCSEL, but run it at 100 gigabit.
So now you have an excellent VCSEL that gives you a lot more performance, and if you use it at half the speed, you get much better bit error rates — the signal-to-noise, or relative intensity noise, drops as well. That’s 100G. But you need more lanes — to get to 1600 you need 16 lanes of 100. And recently something came out called micro-VCSELs.
And that goes even slower, down to 50G — they call it NRZ. So instead of PAM4, which has four levels (0, 1, 2, 3), we go back to the original NRZ, which is 0 and 1. Now you use the entire 0-to-1 signal-to-noise, which again reduces your bit error rate. But you need more channels — 32 channels at 50G to get to 1.6T.
But we’re shipping all three, and all three are in demand depending on whether customers want what they call fast and narrow (8×200); or an LPO — linear drive, no DSP, low power — which is 16×100G; or, if they want really low bit error rate and very low power, the 32×50G NRZ, which they call slow and wide.
We tend to call it “fast and wide” and “faster and narrow.” When you’re in high-speed interconnect, we try not to use “slow” in any of our marketing.
Austin: That’s good, that’s good. Okay, interesting — this is really cool. So you’re saying there are many ways to get to 1.6T. You could have 8×200, which uses PAM4 and requires a lot of DSP and power, but it’s definitely possible. Or 16×100 or 32×50, and you need less DSP for each of those — the 32×50 has much less because it’s NRZ. Yeah, this is all fascinating. So will that approach still hold once you move to 3.2T? Is it going to be that same combination of possibilities?
The Roadmap to 3.2T and 12.8T
Al: Great question — people always ask, what’s the roadmap ahead, what’s the future, is this the end of the road? Okay, 1.6T, VCSELs can do it — but is there a 3.2T? A 6.4T? A 12.8T? I mean, Andy Bechtolsheim — notorious — he’s created an XPO that’s literally going to give you 12.8T in a big pluggable today.
So they’re planning way ahead, because no one has ever told us in the last 30 years, “whoa, we have way too much bandwidth.” We have to have that bandwidth. And exactly like you said — what’s the future? Number one, we can use something called bi-di, bidirectional. Meaning we just add another wavelength — not the complexity of WDM where you have eight or 16 wavelengths like single mode.
We basically just add another wavelength to our existing one. So two wavelengths, passing them in both directions — bidirectional. That doubles the bandwidth without changing anything else, except you add another laser at a different wavelength, and you leverage the entire ecosystem. So from 1.6 to 3.2, we could add another wavelength. The other way, of course, is to double the speed. Can we do 100G NRZ?
That’s in the works. We’re developing 100G NRZ — today is 50G NRZ, but we’re developing 100G NRZ, leveraging our 200 gigabit VCSEL running at 100G NRZ. And in the future, we can go to more channels. The beauty of VCSELs again — surface emitting. Edge emitters can only have a one-dimensional array — a 1×4, 1×8, 1×12 — it just makes a long bar.
But for surface emitting, we can have a two-dimensional array — 2×4, 2×12, 2×16 — and couple all the light very elegantly with an optical fiber bundle. In that case I’m kind of unlimited. I can go up to 64 channels today in a 4×16 connector that’s the size of — let me show you. A 4×16 fiber is this size — here’s my finger. And that has 64 channels in it. If I run them at 200, that gets me to 12.8T. So in essence, the technology of today — without having to go to 400G per lane, which we’re also looking at — but at 200G, with more channels, with more colors (another color for bi-di), you double, you triple, by size. So that roadmap to 12.8T, we believe, is very solid and very clear — without even having to invent any new technology. And then with new technology, it just gets easier, if you can do 400G per lane.
Austin: Sure. Fascinating. So it’s just the same 200G VCSEL over and over — put it in an array and you get more of those. Or are you having to invent a new VCSEL to get the 100G version to run at NRZ?
Al: We’re just starting tests. We believe the 200G VCSEL has the capability to go to 100G NRZ. So it’s not a new VCSEL — it’s just a different coding on the signal coming in, running at NRZ instead of PAM4, to take advantage of the 0-to-1, using the whole signal-to-noise ratio as one bit as opposed to four levels. So that’s the difference.
Lead Times, Yields, and WIN’s Capacity
Austin: Gotcha. Yeah, this goes back to your engineering, pragmatic mindset — taking a Lego block and figuring out different ways to place it, different ways to use it, to unlock this whole roadmap. That’s pretty cool. So you talked about unconstrained gallium arsenide and working with WIN — they’re used to making this stuff, they’ve got all the pizza ovens they need. So if a big hyperscaler comes to PicoJool and says, we want a million of your pizzas — what does that look like? How does that actually happen?
Al: Right. If they want a million VCSELs, we’d typically give them an eight- to ten-week lead time. That’s the basic. We can accelerate it — push and have engineering carry certain wafers — but typically eight to ten weeks on the VCSEL side. You’ll get a wafer, or individually diced VCSELs. If you want transceivers, then that eight weeks tags on a certain number of weeks to package it all into the transceiver.
Those are constrained strictly by the packaging process — not by ordering equipment or building capacity. That ecosystem works, and it leverages the typical cycle time of building out. Typical cycle time: eight weeks for the VCSEL device, then four to six weeks for the module after that. So you’re looking at anywhere from 12 to 16 weeks to get to the full module, starting from an epi reactor growing epi and going all the way through.
And we’ll continue to drive that lower — lead time or cycle time. But also yields, which I didn’t mention much. Yields are: if I make a VCSEL, how many known-good die can I get out of a wafer? The higher the yield — up to 100% — the fewer wafers I have to run, and the higher the capacity of the factory. If every wafer goes through and I get 100%, I need fewer wafers, and therefore less capacity for the demand. Obviously getting to 100% is very hard, but VCSELs have been perfecting that process for many years, for many decades — and now we’re leveraging all of that. It’s not new, it’s not something that has to be established, it’s not based on new technology. That’s very important. WIN has been doing it for about 10 years, since we transferred that for a consumer electronics application back in 2016. They have a capacity of up to a thousand of these wafers per week. And there are about 240,000 VCSELs on each wafer, because they’re really tiny. So that adds up to a million yielded from maybe 10 wafers. The capacity is huge for datacom. So I think we have no worries — once we get to the 200G, the product specs are met with the customer, and reliability qualification is done, then we just ramp readily with WIN, and they’re ready to go.
The Fabless Model — Stay Small, Leverage the Supply Chain
Austin: Nice. Amazing. It’s quite compelling. Normally when people hear “there’s a startup trying to compete in a space with these huge incumbents,” the question is: how’s this startup going to compete? How do they get to market, find customers, build up supply chain? But what I hear you saying is that you’re taking industry veterans with process know-how — similar ways of thinking as competitors, you’ve been in the game a long time — and tapping into an existing supply chain. And at the end of the day, it’s not like you have to win 50 customers; there’s a handful of big customers that would really make a difference for PicoJool if they said yes. But the most important point is the unconstrained gallium arsenide — being able to make a million, 10 wafers with 240,000 on each, whatever you yield, we’re talking millions of VCSELs very quickly. Because across all of semiconductors — memory, CPUs, AI accelerators — there’s so much demand and such constrained supply that, yes, you want to compete on cost and engineering performance, but there’s also a bit of: if it’s good enough and it’s in production and you can install it into my data center, game on. So it feels like you have a strategy that lets you deliver shipped VCSELs as soon as possible.
Al: Yeah, the model has been around for decades in silicon. I’m in Palo Alto, in Silicon Valley. Most chip companies designing integrated circuits, CPUs, GPUs, don’t have their own foundry. A lot of people use Intel; even AMD uses TSMC. AMD is a huge chip company and they don’t have their own foundries today. TSMC, Intel, Global Foundries — many foundries are the factory floor, the clean rooms, of all these startups. So just because of our small startup size doesn’t mean we can’t ship in the millions per month and compete directly with the very large presence of other optical suppliers and competitors. That’s the beauty — we can stay very lean. Our motto is “stay small,” and that has to do with many things — our name is PicoJool, right? Very, very low power, and that’s one of the things driving us. We’re a well-experienced small team, but we get huge benefit by leveraging WIN Semiconductors and working with our supply chain. They’ve got the factories and the clean rooms, and we can ramp very quickly by providing our designs and our unique specialty, then partnering with these large companies that are already shipping — and they just drop-ship. So we don’t need a big company to ship in the millions per month.
Austin: That’s amazing. Definitely punching above your weight — that is awesome. So when is your high-volume ramp targeted for? If I recall, the press release said something —
Ramp Timing — Sampling Now, HVM in Early 2027
Al: Yes, the press release said we’re starting to sample next quarter. And that’s in different flavors — we’ve got customers for the 50G NRZ, the 100G LPO, and the 200G. So all of those begin to sample. And the process from our device to actual product shipment — revenue, in our case — is a period they call qualification, or reliability testing. Everything has to not only meet spec at zero hour, but be predicted to last 10 years, or a number of years, through what they call accelerated aging — they test it at higher temperature and higher bias conditions, then estimate back to normal operating conditions: can it last 10 years in the field? For very small, tier-two customers, that can be as short as three months. But for tier one — because they have much more to lose if there’s an issue with their connection — it takes more than six months to get up and running. So ramping at WIN is available today; but we have to go through this qualification cycle with our customers before they give the orders and everything is approved. So we’ve also said we’ll most likely start ramping in early 2027, next year.
Austin: Okay, got it. Thank you for the education here. So — sampling, then the qualification process, then ramping. And probably, as you’ve been saying throughout, you’re not concerned about the ramping. You had to build the product and let customers kick the tires, and once they say let’s go, it’s off to the races. Okay, awesome. Well, we’ve covered so much — this has been amazing. I’ve learned a lot, and I know the listeners will have too. Is there anything else, any last things about PicoJool, or anything we didn’t talk about that you were hoping to cover?
Mentoring the Next Generation of Photonics Engineers
Al: One thing that’s very interesting to me — as you can see from the image, I’m a very experienced, elderly startup person. One thing to point out: very few people went into hardware and photonics in our space, because young people over the last 25 years — literally since dot-com — came into the workforce more on the application side, the software side. People wanted to go into computer science. So the aging, experienced hardware folks in photonics need to transfer all this knowledge. That’s one of my passions — to bring on the next generation, and the generation after that, for photonics. Because just like VCSELs and other technology, we see many decades ahead, and as I said, no one’s saying “way too much bandwidth.” We see bandwidth demand increasing with robotics and autonomous vehicles and what have you — everything is going to be bit- and connectivity-constrained. So we want to spend time to educate and train. We’re trying to hire hardware engineers, and train young folks — maybe without the experience — to be the VCSEL designers and transceiver designers of the future. That’s really exciting for us, because we’ve got all this knowledge, 10, 20, 30, 40 years, and it feels wonderful to have the hardware excitement again — not only in the markets, but the investment community. Silicon Valley is booming with photonics and hardware. So we don’t take it for granted. It’s a great opportunity, and we definitely want to take young entrepreneurs, young engineers, folks interested in this space, along for the ride — and then they take it from there.
Austin: I love it. Very inspiring, very cool. It’s never been a better time for interconnects, photonics, and optics folks. I love that you industry veterans want to bring up the next generation and give them the opportunity to learn from folks like you — to revitalize, rebuild, make sure we have a reinvigorated workforce, so that for my generation and the generation of my children, they can keep having more and more data moved around, faster and faster.
Al: That’s right. Yeah, really enjoyed our conversation, Austin. Thank you.
Austin: Awesome. Thank you, Al. Appreciate it.