For the third and final presentation in this morning’s first CPU session at Hot Chips 2026, NVIDIA is taking to the lectern to present on Vera, its next-generation server CPU. Based on their new Olympus CPU core architecture, Vera is an in-house Arm server CPU with 88 cores that serves as a critical part of NVIDIA’s upcoming Vera Rubin AI systems. It is also their most ambitious effort yet to expand their overall presence in the server CPU market, as NVIDIA is looking to capture a larger piece of the pie with their specialized-but-powerful CPU. Today’s presentation follows the company’s release of their Vera/Olympus whitepaper last month.
Please note, we are covering this live, so please excuse typos.
NVIDIA Vera CPU at Hot Chips 2026 #
At a high level, Vera is designed to be a very modern and monstrous CPU in virtually every regard. The large chip focuses heavily on IPC over core count, leaving it with 88 CPU cores altogether, and flanked by eight 128-bit LPDDR5X memory controllers. The NVLink-C2C interface on the chip is designed to pair well with NVIDIA’s own Rubin GPUs, but it can also plug in to anything else that implements NVLink-C2C, or to another Vera chip for a 2P pure CPU setup. The successor to NVIDIA’s Grace CPUs, which have backed their server systems for both the Grace Hopper (GH) and Grace Blackwell (GB) generations, Vera is designed to be a significant advancement from Grace in every possible way.
NVIDIA is starting things off by framing this talk about how AI is the most complex computational workload yet. And it is not one task or query, but it is a full workflow that touches multiple tools and types of computation. You cannot just optimize for one use case and win.
Vera Rubin has been built with extreme co-design across hardware and even software. This spans the NVL72, LPX3, Bluefield racks, and others.
NVIDIA has shown off this curve (and similar) a lot over the past year: their performance frontier, the trade-off between token throughput and user interactivity. High batching can maximize token generation, but it makes the response time quite poor. Vera Rubin is meant to push this frontier out in every direction, moving the sweet spot higher in both throughput an interactivity.
And here is another look at how throughput compares to interactivity at various points on the curve. At higher levels of interactivity (higher token rates per user per second), Vera Rubin offers up to 30 times the total throughput of Grace Blackwell. Though it is heavily dependent on where you are on the curve; Grace Blackwell collapsed at an earlier point that Vera Rubin.
And for customers who need more than what Vera Rubin can do on its own with just CPUs and GPUs, NVIDIA now has its Grorq LPX3 racks, which use Groq’s dedicated hardware for decode acceleration to push out the curve farther to allow for very high interactivity rates without performance collapsing.
Here is a quick look at NVIDIA’s performance claims for Groq LPX3. Long-context decode is four times faster than current public services.
Shifting gears over to the Vera CPU, the design point for CPUs has changed over time. Server CPUs no longer look like desktop CPUs with more cores. Meanwhile server economics have favored renting out cores, and thus chip designs for a very large number of cores, but weaker CPU cores overall. But this does not work for AI workflows, where higher single-threaded performance is needed.
To that end, NVIDIA opted for a design with a very high IPC and thus high performance in single-threaded workloads.
A big part of that design philosophy was also on latency. Agents move from task to task; the sooner they can complete one task, the sooner they can move on to the next. Which benefits high IPC architectures like Vera.
Here’s an example of what performance looks like on Vera. Agnetic workloads make for an interesting case as, in the case of browsers, you can run them headless on an agentic system; there is no human that needs to see the output. This also changes the performance profile though, as a headless browser performs quite differently from a traditional browser.
Overall, NVIDIA is pitching Vera as offering 5 innovations that differentiate it from traditional server CPUs: the high IPC, power efficiency, the amount of data it can move, the security/confidential computing, and the overall I/O bandwidth.
Another major promotional point for NVIDIA: how well Vera performs under load versus other CPU architecture. Determinism is a key word for the company here.
Here is a quick look at the Olympus CPU core logical diagram, which we first saw with the NVIDIA whitepaper last month. There is a lot of hardware in each and every core, with massive buffers, a huge 10-wide decode front-end, and an even bigger backend to consume those decoded instructions.
Olympus is agentic-first, but not agentic-only. So NVIDIA made sure to implement a form of SMT into the core for when many threads are needed. Though they went with statically partitioned spatial multithreading, rather than resource sharing across multiple threads in a CPU. NVIDIA is able to get the same level of performance as traditional SMT, but is less susceptible to noise from threads fighting over the same CPU resources.
For their big benchmark reveal last month, NVIDIA took a section of the SPEC CPU 2026 suite that they think maps well to what kinds of workloads an agentic workflow may use. Agentic workloads are close to 1.8x, while data processing workloads are closer to 1.5x. Though NVIDIA is quick to reiterate that these are proxy workloads. Vera is designed to have stable performance at high core counts.
LPDDR5X was the obvious choice for a memory subsystem. It was the most energy efficient choice, and energy efficiency is a key constraint to modern systems.
To build Vera, NVIDIA needed more silicon than could be delivered with a single reticle-limited die. The end result was that they split it up into 6 dies, retaining a monolithic die for the compute cores, but moving the memory and I/O to their own chiplets. NVIDIA uses NVLink-C2C for a link to Rubin GPUs or another Vera CPU in a 2P configuration. The system I/O die has 96 lanes of PCIe/CXL I/O. And all of this sits on top of a single interposer.
Confidential compute is another priority for NVIDIA and its customers. Vera (and Rubin) was designed to offer a full-stack solution for confidential compute across the entire rack. This ensures the system is tamper-proof – at least when used with a suitable software platform, such as NVIDIA’s DOCA software platform.
Implementing it required an intense co-design between the CPU, GPU, and NIC. The GPU checks requests coming in from the CPU, taking advantage of per-core encryption keys.
Vera is designed to work with the most valuable chips in the data center. To support that, the chip has 96 lanes of PCIe and CXL. They use the PCIe lanes to connect to the ConnectX NICs.
In closing, Vera is available as part of NVL72 as well as Vera servers. NV and their partners will be offering both rackscale systems as well as individual servers.
It goes without saying that NVIDIA’s engineers are very proud of what they have accomplished, especially as they are moving to an in-house designed CPU core here, which gave them a chance to not only build the CPU they wanted to build, but to show off some of what they could do.