Via dwglogo.com
The next-generation GPU architecture will use TSMC's 1.6 nm process, 3D die-stacking, and custom high-bandwidth memory to tackle demanding AI workloads.
Nvidia is pushing forward with its Feynman GPU microarchitecture, targeting a 2028 release. The platform will be built on TSMC’s A16 process node, measuring just 1.6 nanometers, and will pack in technologies like 3D die-stacking, backside power delivery, and custom high-bandwidth memory.
What Feynman brings to the table #
CEO Jensen Huang first unveiled the Feynman architecture at GTC 2025, with additional technical details shared at GTC 2026 in March. Named after legendary physicist Richard Feynman, the platform is designed to succeed the Rubin architecture in Nvidia’s roadmap and will pair with a new CPU called Rosa, which follows the current Vera architecture.
Backside power delivery moves power delivery to the back of the chip, freeing up space for data pathways and improving both performance and energy efficiency.
The TSMC bottleneck #
As of March 2026, TSMC’s A16 wafer capacity is fully booked through 2028. Nvidia is reportedly contemplating design changes to certain components of the Feynman platform specifically to navigate these manufacturing constraints.
TSMC plans to ramp A16 production to 20,000 wafers per month by the end of 2027, with further capacity increases expected throughout 2028.
To accelerate the design and verification timeline, Nvidia is leveraging its existing Blackwell GPU technology as a foundation rather than starting from scratch.
Disclosure: This article was edited by Editorial Team. For more information on how we create and review content, see our