Marvell announced its second-generation Structera X CXL memory expanders at the OCP Global Summit, moving the line to six memory channels, four-host sharing, and a PCIe 6.0 x16 host link. The Structera X 3406 drives 18 DDR4 RDIMM slots for up to 9TB behind one controller, and the Structera X 3506 drives 12 DDR5 RDIMM slots for up to 6TB. Both are CXL 3.2, up from four channels on the first-generation 2404 and 2504, and Marvell expects them to sample in the first quarter of 2027.
The four-host fabric is the structural change, because a single Structera X controller can present its DIMMs to up to four hosts at once across up to 256GB/s of aggregate PCIe 6.0 bandwidth, so a tray of DDR4 or DDR5 becomes a shared capacity pool for a group of servers in place of a private expansion card for one. Marvell pitches the pairing at the memory-bound side of inference, where KV cache capacity sets time to first token and how long a context window a server can hold, and at deep learning recommendation models, whose embedding tables typically outgrow the DRAM a socket can address directly.
High-Throughput LZ4 Compression #
The onboard LZ4 engine reaches up to 250GB/s of compression and decompression throughput, five times the previous generation, and Marvell says it yields 2x to 3x more effective memory capacity depending on the workload. For recommendation models, Marvell claims up to 2x higher queries per second and 2x to 3x more effective embedding-table capacity per controller. For LLM serving, it claims 40% to 50% faster time to first token at the same context length, or up to 2x longer supportable context windows at the same latency, in both cases against the first-generation parts. These are vendor results, and we did not run or audit them.
Security Architecture #
Reliability comes from StructGuard, Marvell’s RAS layer with advanced error correction aimed at DRAM device failures. On the data path, the controllers combine post-quantum cryptography, Caliptra 2.0 root of trust, CXL IDE link encryption, and AES-256 memory encryption, which Marvell calls an industry first for post-quantum security on a CXL expander.
The two parts carry over the driver stack and ecosystem validation from the 2404 and 2504, which Marvell says are already shipping to hyperscalers. AMD, Arm, Alibaba, Samsung, and SK hynix all supplied supporting statements, with Samsung and SK hynix pointing to validation of Structera with their DDR parts. Structera X sits alongside Structera A near-memory accelerators and the Photonic Fabric Memory Appliance for pod-level pooling, which Marvell describes as a portfolio running from direct-attach expansion to disaggregated memory. Marvell is demonstrating the 3406 and 3506 at booth B31 through October 15.
Controller Specifications #
| Specification | Structera X 3406 | Structera X 3506 |
|---|---|---|
| Platform Overview | ||
| Interface | CXL 3.2, PCIe 6.0 x16 | CXL 3.2, PCIe 6.0 x16 |
| Host Connectivity | Up to 4 hosts Up to 256GB/s aggregate | Up to 4 hosts Up to 256GB/s aggregate |
| Memory Channels | 6 | 6 |
| Memory Type | DDR4 RDIMM | DDR5 RDIMM |
| DIMM Slots | 18 | 12 |
| Maximum Capacity | 9TB | 6TB |
| Features | ||
| Compression | Inline LZ4, up to 250GB/s | Inline LZ4, up to 250GB/s |
| Security | Post-quantum cryptography Caliptra 2.0 CXL IDE AES-256 memory encryption | Post-quantum cryptography Caliptra 2.0 CXL IDE AES-256 memory encryption |
| RAS | StructGuard advanced error correction | StructGuard advanced error correction |
| Sampling | Q1 2027 | Q1 2027 |