flash
Kioxia has started delivering samples of its tenth generation 3D NAND BiCS chips with 332 layers.
These are 1 Tbit chips formatted in 3 bits per cell (TLC) mode intended for use in building enterprise and data center SSDs. The technology follows on from Kioxia’s BiCS 8 flash with 218 layers. As well as increasing the layer count by 52 percent Kioxia has introduced CMOS directly Bonded to Array (CBA) and On-Pitch Select Gate Drain (OPS) technology. CBA involves making separate logic and NAND cell wafers and then bonding the two together. OPS shortens the bit line and reduces the word line capacitance by removing unused memory holes.
Chip cell density has been increased by improved lateral scaling as well as be adding the extra 114 layers. The 4.8 Gbit/s interface speed is 33 percent faster than BiCS 8. Kioxia says write and read power efficiencies have improved by 18 percent and 30 percent respectively, helping to reduce power consumption.
Kioxia has an intervening BiCS 9 technology which uses BiCS 8, 218-layer, 3D NAND cells with a separate CMOS logic layer providing more performance than the BiCS 8 logic circuitry. The interface speed, at 4.8 Gbit/s s with BiCS 10, is 33 percent faster than BiCS 8 and achieved by using the Toggle DDR6.0 interface and an SCA (Separate Command Address) protocol.
Mass BiCS 10 production is expected to start next year at the Kitakami plant 2 in Iwate Prefecture, Japan. As Sandisk and Kioxia share the output of the cfab through their joint-venture we can expect Sandisk to sample ship BiCS 10 chips pretty soon. The gateway is also open to producing QLC (4 bits/cell) version software the 332-layer technology, increasing chip capacity by a third.
We understand the BiCS 10 technology involves stacking three 100+ layer NAND strings together rather than building a monolithic 332-layer chip.
Kioxia believes that A!I-boosted NAND demand will stay strong as agentic AI spreads and AI-powered robots become popular. CEO Hiroo Ota hinted at production capacity increases as he said: “We will firmly respond to the market’s growth,” at a media event in Japan.
SK Hynix has 321 layers in its ninth generation 3D NAND technology, also using a triple string stack design, while Samsung has 400 with its tenth generation V NAND. As with Kioxia this is made with separate logic and NAND cell wafers and produces a 1 Tbit die. Samsung calling it Cell-on-Periphery (CoP) architecture. Micron is at the 276-layer level. Its future layer-count plans have not been revealed. China’s YMTC is expected to announce 300-layer class technology in the not too distant future.