From what I've pieced together, Marvell's been Google's ASIC partner for years on networking chips and earlier TPU iterations. This new agreement apparently locks in development through the next several TPU generations, possibly including the inference-focused chips Google's been hinting at for cloud customers. The Wall Street Journal broke the story but the specifics are thin — no public roadmap, no tape-out dates, just the dollar figure and "strategic partnership" language. What I'm genuinely curious about: does this signal Google moving further away from Broadcom? Broadcom's been the other big name in Google's custom silicon story, especially on the networking side. Marvell's been gaining share in high-speed SerDes and coherent DSPs for data center interconnects, so maybe Google's consolidating around one partner for both compute and networking IP. Or maybe it's just a capacity play — TSMC advanced packaging is tight, and locking in Marvell's design team ensures Google gets priority.
The TPU v5e (now called Trillium) launched last year with decent inference perf-per-watt numbers. If this deal funds v6 and v7, we're looking at chips that might not tape out until 2026-2027. That's a long horizon in AI years. Makes me wonder if Google's planning for post-transformer architectures or just scaling the current paradigm harder.
Also notable: Marvell stock popped 20% on the news. Market clearly thinks this validates their custom ASIC business model. But for us watching from the outside, the real question is whether Google's internal chips stay internal or if we'll see Trillium v2/v3 offered on GCP with competitive pricing against NVIDIA H200/B200. The cloud AI accelerator market is getting crowded — AWS Trainium2, Azure Maia, Google TPU, plus all the merchant silicon from AMD and Intel.
Anyone have better sources on the actual technical scope? I've seen conflicting reports on whether this includes optical interconnect IP or just the compute die.
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