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DDN says today, a GPU often has to ask the CPU to fetch data for it. DDN and Nvidia are testing a way for the GPU to ask for that data itself, thus cutting out a step and reducing idle time. The new approach uses Nvidia’s SCADA architecture with DDN’s Infinia platform. This technique speeds up data-intensive AI inference and helps companies get more ROI from their infrastructure. When GPUs are waiting for data, companies are paying for compute that is not doing useful work. DDN will demonstrate the working technology at Flash Memory Summit (August 4 – 6).
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Graid Technology will be at FMS 2026 and has reached a new benchmark: 100 million random 512-byte IOPS on a protected RAID 5 volume for GPU-initiated I/O, built from 32 KIOXIA XD8 NVMe SSDs. The result was achieved using SupremeRAID (GPU-powered RAID card) and shows that resilient NVMe storage can now operate at the scale current and future AI deployments require. In benchmark testing with a WholeGraph training workload, this configuration delivered training performance on par with the baseline environment, with no measurable performance compromise. It's also announced a VROC oadmap.
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**Marvell **announced new semiconductor offerings across its AI memory infrastructure portfolio, spanning server-level AI storage, rack-scale CXL memory expansion and pooling, and pod-level optical shared memory.
Bravera SC6 PCIe 6.0 SSD controller doubles the PCIe gen 5 version’s performance and enables more KV cache to move from high-bandwidth memory to SSD. It supports NAND from multiple suppliers. More information
hereand it’s expected to begin sampling in Q4 2026.Structera X memory expansion for rack-level memory expansion and CXL-based pooling. More information
here.Photonic Fabric memory modules. Photonic Fabric NIC and Photonic Fabric chiplets are foundational elements of a multi-rack optical shared-memory architecture for AI inference. creates a new shared-memory tier across multiple XPUs and racks up to 50 meters, enabling up to 32TB of warm KV cache offload with high bandwidth and extremely low latency. By expanding memory access across AI clusters and enabling KV cache to be loaded from a shared memory tier rather than storage, Photonic Fabric helps increase inference throughput, support larger models and longer context lengths, and increase token efficiency by delivering up to 2-3x higher token throughput within existing data center footprints and power envelopes. Visit the Marvell blog for more information
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At FMS, Nvidia announced it is open sourcing its cuFile application programming interfaces (APIs) — and the vertical storage software stack underneath them — which let GPUs, not just CPUs, read from and write to storage directly. Using hundreds of thousands of GPU threads, fast high-bandwidth memory and other methodologies, cuFile enables securely accessing data from storage in just microseconds. This represents how the industry is unifying a security-first storage stack based on Linux best practices, providing interoperability between GPUs and data.
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Nvidia says it and storage industry leaders are optimizing memory and storage solutions through an initiative called Storage-Next. The Nvidia-driven initiative brings together storage makers, controller vendors, thermal design, cooling and orchestration operators, and standards bodies to align on how GPU-driven storage should behave — then turn these advancements into interoperable, open industry standards. Storage-Next includes over 40 leading storage and flash vendors — including DDN, Kioxia and Micron — each contributing to the next generation of AI storage technologies with Nvidia.
The initiative is grounded in accelerated data access for large AI datasets. To support this, Nvidia offers SCADA (scaled, accelerated data access), a framework that lets massively parallel GPUs pull only the data necessary for the application directly from storage into their own high-speed memory.
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Samsung unveiled concept models of zHBM and zNAND-O, presenting its vision for the next generation of 3D memory architectures.
zHBM presents a new memory architecture that vertically stacks HBM directly above AI accelerators, moving beyond conventional designs in which HBM is positioned alongside the processor. Talking about zHBM performance, Leno Park, Samsung's VP of Product Planning and NAND Solutions, said in a briefing: "Our target is to deliver maximum eight times better than HBM5 and also the performance per watt will be improved three times." Thermal resistance will improve by 0.5.
zHBM also supports customer-specific designs, enabling customized IP to be integrated into the interlayer between the memory and AI accelerator to expand memory capacity and enhance accelerator performance.
The zHBM technology uses wafer on wafer integration combined with hybrid copper bonding (HCB) and direct copper to copper connection. Data movement length is reduced. TSV diameter and pitch are reduced to approximately one-third, increasing TSV density 10 times. Also, Park said: "We're going to eliminate the use of complex, high-speed SERDES circuitry.
There are challenges around heat dissipation, with Park saying: "We are in … discussion how we're going to make it work to support 1,000 tokens per second by 2030."
**zNAND-O **is a next-generation high-performance NAND architecture available in four- and eight-layer versions. By combining high space efficiency, improved I/O performance, and low latency, zNAND-O is optimized for edge AI environments supporting real-time, data-intensive AI applications.
V10 BV-NAND, with 400+ layers, has a Bonding V-NAND architecture. By applying wafer bonding technology to stack memory cells, Samsung has increased memory density by approximately 58% over the previous generation (V9). V10 BV-NAND also improves read, write and I/O performance over V9
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Sandisk and SK Hynix released the HBF (High Bandwidth Flash) technical specification through the Open Compute Project (OCP), to drive HBF standardization for the AI inference era. The spec was developed through the HBF technology workstream under OCP, with Sandisk and SK hynix serving as primary contributors. Google and Tenstorrent joined as consortium members during this process, contributing to technology validation and the establishment of the standard.
It defines system interface, electrical and other technical guidelines for designing systems that interact with and use HBF technology, including basic performance expectations, the xPU-HBF host interface, reliability and packaging guidance for an HBF die stack, and a software user guide for read and write operations.
A YouTube video entitled "SK hynix Unveils First HBF Standard Specifications with Sandisk" talks about HBF in a great hurry.
SK Hynix's said HBF capacity specifications cover up to 512GB based on two stack configurations (8-high and 16-high NAND dies). Bandwidth is categorized into three grades (Grade1~3), delivering scalable performance from approximately 0.4TB/s to 3.0TB/s.
HBF technology adopts UCIe, an industry standard connection interface, as the interconnect linking HBF technology and processors. This lays the groundwork to flexibly integrate HBF technology across different processor types, including GPUs and CPUs.
The spec provides companies and developers designing AI inference systems and accelerators with a common technical framework for incorporating HBF technology, alongside HBM, where larger, near-compute memory capacity and higher bandwidth are needed to improve power and performance metrics and help reduce total cost of ownership.
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Sandisk and Kioxia unveiled BiCS 10 QLC (4 bits/cell) 3D NAND technology, featuring;
332‑layer architecture and optimized floorplan design deliver up to 60% increase in bit density, achieving >37 Gb/mm compared to the 8th-generation.
4.8 Gb/s NAND interface enabled by Toggle DDR6.0 and the Separate Command Address (SCA) protocol to unlock the full potential of fast interface.
CMOS‑directly‑Bonded‑to‑Array (CBA) architecture enhances density scaling, performance, and manufacturing efficiency.
Power‑Isolated Low‑Tapped Termination (PI‑LTT) improving I/O data-out transfer power efficiency.
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SK Hynix will reveal tenth-generation (V10) 375-layer so-called 4D NAND wafer and products, which are currently under development. The 375-layer 4D NAND improves performance per watt by 2.5 times compared to the previous generation, making it optimized for AI infrastructure environments like data centers that demand high power efficiency and performance. The company plans to initiate mass production of high-performance, high capacity eSSDs based on the 375-layer 4D NAND early next year.
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XCENA is demonstrating a CXL memory pool of up to 20 TB using memory pooling systems at FMS 2026. It’s also presenting a KV cache sharing demonstration showing how AI inference infrastructure can use shared memory resources more efficiently, and it’s showcasing two MX1 products at FMS 2026:
MX1 Compute pairs CXL-based memory expansion with near-data processing enabled by 2,048 RISC-V cores, placing compute directly adjacent to memory so data-intensive operations run where data resides. By eliminating unnecessary data movement between CPUs and memory, MX1 Compute improves AI inference performance and system efficiency, while lowering power consumption.MX1 Expand provides eight DRAM slots and supports hyperscalers' needs for DRAM reuse and server scale-up, giving operators a flexible, cost-efficient path to expanding memory resources across AI infrastructure.
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